XPLA3 Datasheet, PDF(4/11 Page) Xilinx, Inc – Excellent pin retention during design changes

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XPLA3 Datasheet, PDF (4/11 Pages) Xilinx, Inc – Excellent pin retention during design changes

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CoolRunnerâ¢ XPLA3 CPLD

From P-term

From PLA OR Term

To Combinatorial Path

and Register Input

Figure 3: Variable Function Multiplexer

FoldBack NANDs

XPLA3 utilizes FoldBack NANDs to increase the effective

product term width of a programmable logic device. These

structures effectively provide an inverted product term to be

used as a logic input by all of the local product terms. Refer

to Figure 4 for an example of this technique. .

PT1

PT2

PT3

A#B#C

PT4

To MC

!A & !B & !C

ds012_04_123099

Figure 4: Basic FoldBack NAND Structure

As seen in Figure 4, the output signal is determined by the

following equation:

MC logic = PT1 # PT2 # PT3 # (PT4) &(A # B # C)

ds012_03_121699

Macrocell Architecture

Figure 5 shows the architecture of the macrocell used in

the CoolRunner XPLA3. Any macrocell can be reset or pre-

set on power-up. Each macrocell register can be config-

ured as a D-, T-, or Latch-type flip-flop, or combinatorial

logic function. Each of these flip-flops can be clocked from

any one of eight sources. There are two global synchro-

nous clocks that are derived from the four external clock

pins. There is one universal clock signal. The clock input

signals CT[4:7] (Local Control Terms) can be individually

configured as either a PRODUCT term or SUM term equa-

tion created from the 36 signals available inside the logic

block..

There are two feedback paths to the ZIA: one from the

macrocell, and one from the I/O pin. When the I/O pin is

used as an output, the output buffer is enabled, and the

macrocell feedback path can be used to feed back the logic

implemented in the macrocell. When an I/O pin is used as

an input, the output buffer will be 3-stated and the input sig-

nal will be fed into the ZIA via the I/O feedback path. The

logic implemented in the buried macrocell can be fed back

to the ZIA via the macrocell feedback path.

If the macrocell is configured as an input, there is a path to

the register to provide a fast input setup time.

DS012 (v1.1) March 3, 2000

www.xilinx.com

1-800-255-7778

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