XPLA3 Datasheet, PDF (7/11 Pages) Xilinx, Inc – Excellent pin retention during design changes

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CoolRunner™ XPLA3 CPLD
JTAG Testing Capability
JTAG is the commonly used acronym for the Boundary
Scan Test (BST) feature defined for integrated circuits by
IEEE Standard 1149.1. This standard defines input/output
pins, logic control functions, and commands that facilitate
both board and device level testing without the use of spe-
cialized test equipment. XPLA3 devices use the JTAG
Interface for In-System Programming/Reprogramming.
The full JTAG command set is implemented (see Table 1),
including the use of a port enable signal.
As implemented in XPLA3, the JTAG Port includes four of
the five pins (refer to Table 2) described in the JTAG speci-
fication: TCK, TMS, TDI, and TDO. The fifth signal defined
by the JTAG specification is TRST (Test Reset). TRST is
considered an optional signal, since it is not actually
required to perform BST or ISP. The XPLA3 saves an I/O
pin for general purpose use by not implementing the
optional TRST signal in the JTAG interface. Instead, the
XPLA3 supports the test reset functionality through the use
of its power-up reset circuit, which is included in all Cool-
Runner CPLDs. It should be noted that the pins associated
with the JTAG Port should connect to an external pull-up
resistor (typical 10K) to keep the JTAG signals from floating
when they are not being used.
The Port Enable pin is used to reclaim TMS, TDO, TDI, and
TCK for JTAG ISP programming if the user has defined
these pins as general purpose I/O during device program-
ming. For ease of use, XPLA3 devices are shipped with
the JTAG port pins enabled. Please note that the Port
Enable pin must be low logic level during the power-up
sequence for the device to operate properly.
During device programming, the JTAG ISP pins can be left
as is or reconfigured as user specific I/O pins. If the JTAG
ISP pins have been used for I/O pins, simply applying high
logic level to the Port Enable pin converts the JTAG ISP
pins back to their respective programming function and the
device can be reprogrammed. After completing the desired
JTAG ISP programming function, simply return Port Enable
to Ground. This will re-establish the JTAG ISP pins to their
respective I/O function. Note that reconfiguring the JTAG
port pins as I/Os makes these pins non-JTAG ISP func-
tional.
The XPLA3 family allows the macrocells associated with
these pins to be used as buried logic when the JTAG/ISP
function is enabled.
Table 1: XPLA3 Low-level JTAG Boundary-scan Commands
Instruction
(Instruction Code)
Register Used
Sample/Preload
(00010)
Boundary-scan Register
Extest
(00000)
Boundary-scan Register
Bypass
(11111)
Bypass Register
Idcode
(00001)
Boundary-scan Register
High-Z
(00101)
Bypass Register
Intest
(00011)
Boundary-scan Register
Description
The mandatory Sample/Preload instruction allows a snapshot of the normal operation
of the component to be taken and examined. It also allows data values to be loaded
into the latched parallel outputs of the Boundary-scan Shift Register prior to selection
of the other boundary-scan test instructions.
The mandatory Extest instruction allows testing of off-chip circuitry and board level
interconnections. Data would typically be loaded onto the latched parallel outputs of
Boundary-scan Shift Register using the Sample/Preload instruction prior to selection
of the Extest instruction.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through the selected device to adjacent devices during
normal device operation. The Bypass instruction can be entered by holding TDI at a
constant high value and completing an Instruction-scan cycle.
Selects the Idcode register and places it between TDI and TDO, allowing the Idcode
to be serially shifted out of TDO. The Idcode instruction permits blind interrogation of
the components assembled onto a printed circuit board. Thus, in circumstances where
the component population may vary, it is possible to determine what components exist
in a product.
The High-Z instruction places the component in a state which all of its system logic
outputs are placed in an inactive drive state (e.g., high impedance). In this state, an
in-circuit test system may drive signals onto the connections normally driven by a
component output without incurring the risk of damage to the component. The High-Z
instruction also forces the Bypass Register between TDI and TDO
The Intest instruction selects the boundary scan register preparatory to applying tests
to the logic core of the device. This permits testing of on-chip system logic while the
component is already on the board
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