DS670 Datasheet, PDF (9/11 Pages) Xilinx, Inc – Low-power CMOS EPROM process

QPRO Family of XC1700E Configuration PROMs
AC Characteristics Over Operating Condition When Cascading
X-Ref Target - Figure 4
RESET/OE
CE
CLK
DATA
(First PROM)
CEO
(First PROM)
T_OOE
First
Bit
T_CDF
Last
Bit
T_OCK
T_OCE
T_OCE
CE
(Cascaded
PROM)
DATA
(Cascaded
PROM)
T_CE
First
Bit
n –1 n
T_CE
n n +1
Figure 4: AC Characteristics Over Operating Condition When Cascading
Last
Bit
DS670_04_120210
Table 9: AC Characteristics Over Operating Condition When Cascading⁽¹⁾⁽²⁾
Symbol
Description
T_CDF
T_OCK
T_OCE
T_OOE
CLK to data float delay⁽³⁾⁽⁴⁾
CLK to CEO delay⁽³⁾
CE to CEO delay⁽³⁾
RESET/OE to CEO delay⁽³⁾
XC1765E
Min Max
–
50
–
65
–
45
–
40
XC17256E
Min Max
–
50
–
30
–
35
–
30
Notes:
1. AC test load = 50 pF
2. All AC parameters are measured with V_IL = 0.0V and V_IH = 3.0V.
3. Guaranteed by design, not tested.
4. Float delays are measured with 5 pF AC loads. Transition is measured at ±200mV from steady state active levels.
Units
ns
ns
ns
ns
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
9