DS670 Datasheet, PDF (3/11 Pages) Xilinx, Inc – Low-power CMOS EPROM process

QPRO Family of XC1700E Configuration PROMs
PROM Pinouts
Table 1: PROM Pinouts
Pin Name
DATA
CLK
RESET/OE (OE/RESET)
CE
GND
CEO
V_PP
V_CC
Capacity
Pin Number
1
2
3
4
5
6
7
8
Table 2: Capacity
Devices
XC1765E
XC17256E
Configuration Bits
65,536
262,144
Number of Configuration Bits, Including Header, for Xilinx FPGAs and Compatible PROMs
Table 3: Number of Configuration Bits, Including Header, for Xilinx FPGAs and Compatible PROMs
Device
Configuration Bits
PROM
XC3000/A series
14,819 to 94,984
XC1765E to XC17256E
XC4000 series
95,008 to 247,968
XC17256E
XQ4005E
95,008
XC17256E
XQ4010E
178,144
XC17256E
XQ4013E
247,968
XC17256E
Controlling PROMs
Connecting the FPGA device with the PROM.
• The DATA output(s) of the PROM(s) drives the D_IN input of the lead FPGA device.
• The Master FPGA CCLK output drives the CLK input(s) of the PROM(s).
• The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any).
• The RESET/OE input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures
that the PROM address counter is reset before the start of any reconfiguration, even when a reconfiguration is initiated
by a V_CC glitch. Other methods—such as driving RESET/OE from LDC or system reset—assume the PROM internal
power-on-reset is always in step with the FPGA’s internal power-on-reset. This might not be a safe assumption.
• The PROM CE input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the
D_IN pin.
• The CE input of the lead (or only) PROM is driven by the DONE output of the lead FPGA device, provided that DONE
is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during
user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an
unnecessary supply current of 10 mA maximum.
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
3