DS670 Datasheet, PDF (5/11 Pages) Xilinx, Inc – Low-power CMOS EPROM process

X-Ref Target - Figure 2
V_CC
D_OUT
FPGA
MODES⁽¹⁾
RESET
RESET
D_IN
CCLK
DONE
INIT
QPRO Family of XC1700E Configuration PROMs
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
V_CC
3.3V
V_CC
V_PP
DATA
CLK
PROM
CE
CEO
OE/RESET
DATA
CLK
Cascaded
Serial
Memory
CE
OE/RESET
CCLK
(Output)
D_IN
D_OUT
(Output)
Notes:
1. For mode pin connections, refer to the appropriate FPGA data sheet.
2. The one-time-programmable PROM supports automatic loading of configuration programs.
3. Multiple devices can be cascaded to support additional FPGAs.
4. An early DONE inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active.
Figure 2: Master Serial Mode
ds670_02_120210
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
5