DS633 Datasheet, PDF (9/10 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

PLB to FSL Bridge v1.00a
Table 12: PLB to FSL Bridge Read Control Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0 - C_FSL_DWIDTH
-1
RDCTRL
Read
-
Read register to get control word from the
Slave FSL interface on the bridge
PLB to FSL Bridge Status Register (STATUS)
The PLB to FSL Bridge Status Register contains the current status of the Master and Slave FSL interfaces. The
register is read only and a write request issued to STATUS will be ignored. Bit assignment in the STATUS register
is described in Table 14.
Table 13: Status Register
0
Reserved
Ctrl
28
29
Full Empty
30
31
Table 14: PLB to FSL Bridge Status Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0 - 28
Reserved
Reserved for future use
Indicates the current status of the Slave FSL
29
Slave FSL
Control
Read
’0’
control bit
’0’ = FSL_S_Control bit is ’0’
’1’ = FSL_S_Control bit is ’1’
Indicates the current status of the Master FSL
FIFO
30
Full
Read
’0’
’0’ = There is room for more data
’1’ = The FIFO is full, any attempts to write
data will be ignored and generate an error
Indicates the current status of the Slave FSL
FIFO
31
Empty
Read
’1’
’0’ = There is data available
’1’ = The FIFO is empty, any attempts to read
data will be ignored and generate an error
PLB to FSL Bridge Error Register (ERROR)
The PLB to FSL Bridge Error Register contains the error flags for PLB accesses to/from the master and slave FSL
interfaces. The error register will be cleared at read, this means that all bits are sticky and that they indicate any
errors that occurred since last time the error register was read. The register is read only and a write request issued
to ERROR will be ignored. Bit assignment in the ERROR register is described in Table 16.
Table 15: Error Register
0
Reserved
Ctrl
28
29
Full Empty
30
31
DS633 July, 4, 2007
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Product Specification