DS633 Datasheet, PDF (10/10 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

PLB to FSL Bridge v1.00a
Table 16: PLB to FSL Bridge Error Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0 - 28
Reserved
Reserved for future use
Indicates if there has been a mismatch
between using RDDATA and RDCTRL with
29
Control Error
Read
’0’
the FSL_S_Control bit since the error register
was last read
’0’ = No mismatch has occurred
’1’ = One or more mismatches has occurred
Indicates if there has been any attempts to
write to the WRDATA or WRCTRL registers
while the Full flag was asserted since the error
30
Full Error
Read
’0’
register was last read
’0’ = No error has occurred
’1’ = One or more attempts to write while FSL
link was full
Indicates if there has been any attempts to
read from the RDDATA or RDCTRL registers
while the Empty flag was asserted since the
31
Empty Error
Read
’0’
error register was last read
’0’ = No error has occurred
’1’ = One or more attempts to read while FSL
link was empty
Design Implementation
Target Technology
The intended target technology is Spartan and Virtex FPGAs.
Reference Documents
• IBM CoreConnect^™128-Bit Processor Local Bus, Architectural Specification (v4.6).
Revision History
Date
07/04/2007
Version
1.0
Initial Xilinx release.
Revision
10
www.xilinx.com
DS633 July, 4, 2007
Product Specification