DS633 Datasheet, PDF (5/10 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

PLB to FSL Bridge v1.00a
resources required by the system only and that operates with the best possible performance. The features that can
be parameterized in the PLB to FSL Bridge design are as shown in Table 2.
Table 2: PLB to FSL Bridge Design Parameters
Generic Feature/Description Parameter Name
Allowable Values
Default
Value
VHDL
Type
System Parameter
G1
Target FPGA family
C_FAMILY
spartan3e, spartan3,
spartan3a,
spartan3adsp,
spartan3an, virtex2,
virtex2pro, virtex4,
virtex5
virtex4
string
PLB Parameters
G2
PLB Base Address
C_BASEADDR
Valid Address^[1]
None^[3]
std_logic_
vector
G3
PLB High Address
C_HIGHADDR
Valid Address^[2]
None^[3]
std_logic_
vector
G4
PLB least significant
address bus width
C_SPLB_AWIDTH
32
32
integer
G5
PLB data width
C_SPLB_DWIDTH
32, 64, 128
32
integer
G6
Selects point-to-point or
shared bus topology
C_SPLB_P2P
0 = Shared Bus
Topology
1 = Point-to-Point Bus
0
Topology^[4]
integer
G7
PLB Master ID Bus Width
C_SPLB_MID_
WIDTH
log₂(C_SPLB_NUM_
MASTERS) with a
minimum value of 1
1
integer
G8
Number of PLB Masters
C_SPLB_NUM_
MASTERS
1 - 16
1
integer
G9
Support Bursts
C_SPLB_SUPPORT
_BURSTS
0
0
integer
G10
Width of the Slave Data C_SPLB_NATIVE_
Bus
DWIDTH
32
32
integer
PLB to FSL Bridge Parameters
G11
The number of data bits
in the FSL interfaces
C_FSL_DWIDTH
32
32
Integer
G12
If the control bit shall be
used
C_USE_CONTROL
0-1
1
Integer
Notes:
1. The user must set the values. The C_BASEADDR must be a multiple of the range, where the range is
C_HIGHADDR - C_BASEADDR + 1.
2. C_HIGHADDR - C_BASEADDR must be a power of 2 greater than equal to C_BASEADDR + 0xF.
3. No default value will be specified to insure that the actual value is set, i.e., if the value is not set, a compiler
error will be generated.
4. Value of ’1’ is not supported in this core.
DS633 July, 4, 2007
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5
Product Specification