DS633 Datasheet, PDF (2/10 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

PLB to FSL Bridge v1.00a
Functional Description
The PLB to FSL Bridge translates PLB accesses to FSL master and slave requests.
PLB to FSL Bridge I/O Signals
The PLB to Bridge FSL I/O signals are listed and described in Table 1.
Table 1: PLB to FSL Bridge I/O Signal Description
Port
Signal Name
Interface I/O
Initial
State
System Signals
P1 SPLB_Clk
System
I
-
P2 SPLB_Rst
System
I
-
PLB Interface Signals
P3 PLB_ABus[0:31]
PLB
I
-
P4 PLB_PAValid
PLB
I
-
P5
PLB_masterID[0:
C_SPLB_MID_WIDTH - 1]
PLB
I
-
P6 PLB_RNW
PLB
I
-
P7
PLB_BE[0:
(C_SPLB_DWIDTH/8) - 1]
PLB
I
-
P8 PLB_size[0:3]
PLB
I
-
P9 PLB_type[0:2]
PLB
I
-
P10
PLB_wrDBus[0:
C_SPLB_DWIDTH - 1]
PLB
I
-
Unused PLB Interface Signals
P11 PLB_UABus[0:31]
PLB
I
-
P12 PLB_SAValid
PLB
I
-
P13 PLB_rdPrim
PLB
I
-
P14 PLB_wrPrim
P15 PLB_abort
P16 PLB_busLock
P17 PLB_MSize[0:1]
P18 PLB_lockErr
P19 PLB_wrBurst
P20 PLB_rdBurst
P21 PLB_wrPendReq
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
Description
PLB clock
PLB reset, active high
PLB address bus
PLB primary address valid
PLB current master identifier
PLB read not write
PLB byte enables
PLB size of requested transfer
PLB transfer type
PLB write data bus
PLB upper address bits
PLB secondary address valid
PLB secondary to primary read
request indicator
PLB secondary to primary write
request indicator
PLB abort bus request
PLB bus lock
PLB data bus width indicator
PLB lock error
PLB burst write transfer
PLB burst read transfer
PLB pending bus write request
2
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DS633 July, 4, 2007
Product Specification