DS633 Datasheet, PDF (6/10 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

PLB to FSL Bridge v1.00a
Allowable Parameter Combinations
The address range specified by C_BASEADDR and C_HIGHADDR must be a power of 2, and must be at least
0xF.
For example, if C_BASEADDR = 0xE0000000, C_HIGHADDR must be at least = 0xE000000F.
PLB to FSL Bridge Parameter - Port Dependencies
The dependencies between the PLB to FSL Bridge core design parameters and I/O signals are described in
Table 3. In addition, when certain features is deselected, the related logic will no longer be a part of the design.
The unused input and output signals are set to a specified value.
Table 3: PLB to FSL Bridge Parameter-Port Dependencies
Generic
or Port
Name
Affects Depends Relationship Description
Design Parameters
G5 C_SPLB_DWIDTH
P7, P10, P33
-
Affects the number of bits in data
bus
G7 C_SPLB_MID_WIDTH
This value is calculated as:
P5
G8
log₂(C_SPLB_NUM_MASTERS)
with a minimum value of 1
G8 C_SPLB_NUM_MASTERS
P36, P37,
P38, P42
-
Affects the number of PLB masters
G11 C_FSL_DWIDTH
P44, P49
-
Affects the number of bits in data
bus
I/O Signals
P5
PLB_masterID[0:
C_SPLB_MID_WIDTH - 1]
-
G7
Width of the PLB_masterID varies
according to C_SPLB_MID_WIDTH
P7
PLB_BE[0:
(C_SPLB_DWIDTH/8) -1]
-
G5
Width of the PLB_BE varies
according to C_SPLB_DWIDTH
P10
PLB_wrDBus[0:
C_SPLB_DWIDTH - 1]
-
G5
Width of the PLB_wrDBus varies
according to C_SPLB_DWIDTH
P33
Sl_rdDBus[0:
C_SPLB_DWIDTH - 1]
-
G5
Width of the Sl_rdDBus varies
according to C_SPLB_DWIDTH
P36
Sl_MBusy[0:
C_SPLB_NUM_MASTERS - 1]
-
Width of the Sl_MBusy varies
G8
according to
C_SPLB_NUM_MASTERS
P37
Sl_MWrErr[0:
C_SPLB_NUM_MASTERS - 1]
-
Width of the Sl_MWrErr varies
G8
according to
C_SPLB_NUM_MASTERS
P38
Sl_MRdErr[0:
C_SPLB_NUM_MASTERS - 1]
-
Width of the Sl_MRdErr varies
G8
according to
C_SPLB_NUM_MASTERS
6
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DS633 July, 4, 2007
Product Specification