DS633 Datasheet, PDF (7/10 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

PLB to FSL Bridge v1.00a
Table 3: PLB to FSL Bridge Parameter-Port Dependencies (Contd)
Generic
or Port
Name
Affects Depends Relationship Description
P42
Sl_MIRQ[0:
C_SPLB_NUM_MASTERS - 1]
-
Width of the Sl_MIRQ varies
G8
according to
C_SPLB_NUM_MASTERS
P44 FSL_M_Data
G11
Width of the FSL_M_Data varies
according to C_FSL_DWIDTH
P49 FSL_S_Data
G11
Width of the FSL_S_Data varies
according to C_FSL_DWIDTH
PLB to FSL Bridge Register Descriptions
Table 4 shows all the PLB to FSL Bridge registers and their addresses.
Table 4: PLB to FSL Bridge Registers
Base Address +
Offset (hex)
Register Name
C_BASEADDR + 0x0 WRDATA
C_BASEADDR + 0x4 WRCTRL
C_BASEADDR + 0x8 RDDATA
C_BASEADDR + 0xC RDCTRL
C_BASEADDR + 0x10 STATUS
C_BASEADDR + 0x14 ERROR
C_BASEADDR + 0x18 Reserved
C_BASEADDR + 0x1C Reserved
Access Default
Type Value (hex)
Description
Write
N/A
Write Data address. Write only.
Write
N/A
Write Control address. Write only.
Read
N/A
Read Data address. Read only
Read
N/A
Read Control address. Read only
Read
0x1
Status flags for PLB to FSL Bridge.
Read only.
Read
0x0
Error flags, clear on read. Read
only.
-
-
Reserved for future use
-
-
Reserved for future use
PLB to FSL Bridge Write Data Register (WRDATA)
Writing to this register will result in a write on the Master FSL Interface if the FSL_M_Full flag is not asserted.
The FSL_M_Control bit will be set to 0 when writing to this register. The register is write only and a read request
issued to WRDATA will be ignored. Bit assignment in the WRDATA register is described in Table 6.
Table 5: Write Data register
0
WRDATA
C_FSL_DWIDTH-1
Table 6: PLB to FSL Bridge Write Data Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0 - C_FSL_DWIDTH
-1
WRDATA
Write
-
Write register to transfer data word to the
Master FSL interface on the bridge
DS633 July, 4, 2007
www.xilinx.com
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Product Specification