DS633 Datasheet, PDF (4/10 Pages) Xilinx, Inc – PLB interface is based on PLB v4.6 specification

PLB to FSL Bridge v1.00a
Table 1: PLB to FSL Bridge I/O Signal Description (Contd)
Port
Signal Name
Interface I/O
Initial
State
P44 FSL_M_Data
MFSL
O
0
P45 FSL_M_Control
MFSL
O
0
P46 FSL_M_Write
P47 FSL_M_Full
P48 FSL_S_Clk
P49 FSL_S_Data
P50 FSL_S_Control
P51 FSL_S_Read
P52 FSL_S_Exists
MFSL
O
0
MFSL
I
N/A
FSL Slave Interface Signals
SFSL
O
N/A
SFSL
I
N/A
SFSL
I
N/A
SFSL
O
0
SFSL
I
N/A
Description
The data output to the master
interface of a FSL bus
Single bit control signal that is
propagated along with the data.
Transmission of the control bit
occurs when
C_USE_CONTROL is set to 1
(default). If the control bit is not
used by the slave,
C_USE_CONTROL can be set
to 0 to save area
Output signal that is asserted
when the data shall be written to
the FSL link
Input signal from the master
interface of a FSL bus indicating
that the FIFO is full.
This port provides the output
clock to a master interface of a
FSL bus when implemented in
the asynchronous mode. This is
the same as SPLB_Clk
The data input bus from the
slave interface of a FSL bus
Single bit control that is
propagated along with the data
when C_USE_CONTROL is set
to 1
Output signal that is asserted
when the data is read from a FSL
link
Input signal from FSL bus
indicating that data is available
PLB to FSL Bridge Design Parameters
To allow the user to obtain a PLB to FSL Bridge that is uniquely tailored for the system, certain features can be
parameterized in the PLB to FSL Bridge design. This allows the user to configure a design that utilizes the
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DS633 July, 4, 2007
Product Specification