DS803 Datasheet, PDF (8/8 Pages) Xilinx, Inc – Modeled as a bus bridge in EDK

LogiCORE™ IP AXI to AXI Connector (v1.00.a)
In addition to the parameters listed in this table, there are also inferred parameters for each AXI interface in the EDK
tools. Through the design, these inferred parameters control the behavior of the AXI Interconnect. For a complete
list of the interconnect settings related to each AXI interface, see the AXI Interconnect IP Data Sheet (DS768).
The tools set the default values of inferred parameters C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE and
C_INTERCONNECT_S_AXI_READ_ACCEPTANCE:
• To 8, when C_S_AXI_PROTOCOL = “AXI4” or “AXI3”
• To 1, when C_S_AXI_PROTOCOL = “AXI4LITE”
The user can override each of these. The same values are then observed as inferred parameters
C_INTERCONNECT_M_AXI_WRITE_ISSUING and C_INTERCONNECT_M_AXI_READ_ISSUING, respectively, by the SI
of the downstream interconnect.
References
• http://www.xilinx.com/ipcenter/axi4.htm
• AXI Interconnect IP Data Sheet (DS768)
• AXI Reference Guide (UG761)
Revision History
The following table shows the revision history for this document:
Date
09/21/2010
Version
1.0
Initial Xilinx release.
Description of Revisions
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DS803 September 21, 2010
www.xilinx.com
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Product Specification