DS803 Datasheet, PDF (7/8 Pages) Xilinx, Inc – Modeled as a bus bridge in EDK

Table 4: Design Parameters (Cont’d)
Parameter Name
C_S_AXI_SUPPORTS_READ
C_S_AXI_SUPPORTS_WRITE
C_S_AXI_SUPPORTS_USER_SIGNALS
C_S_AXI_AWUSER_WIDTH
C_S_AXI_ARUSER_WIDTH
C_S_AXI_BUSER_WIDTH
C_S_AXI_RUSER_WIDTH
C_S_AXI_WUSER_WIDTH
C_S_AXI_SUPPORTS_NARROW_BURST
C_S_AXI_NUM_ADDR_RANGES
C_S_AXI_RNG0-15_BASEADDR
C_S_AXI_RNG0-15_HIGHADDR
LogiCORE™ IP AXI to AXI Connector (v1.00.a)
Default
Value
1
1
0
1
1
1
1
1
1
1
0xFFFFFFFF
0x00000000
Allowable
Values
Integer
(0, 1)
Integer
(0, 1)
Integer
(0, 1)
Integer
(1-2147483647)
Integer
(1-2147483647)
Integer
(1-2147483647)
Integer
(1-2147483647)
Integer
(1-2147483647)
Integer
(0, 1)
Integer
(1-16)
0x1000
0x1000
Description
Indicates to both interconnects whether
Read transactions need to be
propagated. Default value set by tools
based on connectivity map of upstream
interconnect; user may override. (Same
value is observed by both
interconnects.)
Indicates to both interconnects whether
Write transactions need to be
propagated. Default value set by tools
based on connectivity map of upstream
interconnect; user may override. (Same
value is observed by both
interconnects.)
Indicates whether USER signals need to
be propagated. (Same value is observed
by both interconnects.)
Width of AWUSER signals (both S and
M interfaces; valid only when
C_S_AXI_SUPPORTS_USER_SIGNALS = 1.)
Width of ARUSER signals (both S and M
interfaces; valid only when
C_S_AXI_SUPPORTS_USER_SIGNALS = 1)
Width of BUSER signals (both S and M
interfaces; valid only when
C_S_AXI_SUPPORTS_USER_SIGNALS = 1)
Width of RUSER signals (both S and M
interfaces; valid only when
C_S_AXI_SUPPORTS_USER_SIGNALS = 1)
Width of WUSER signals (both S and M
interfaces; valid only when
C_S_AXI_SUPPORTS_USER_SIGNALS=1)
Indicates to both interconnects whether
narrow burst transactions are expected
to be propagated. Default value set by
tools based on connectivity map of
upstream interconnect; user may
override. (Same value is observed by
both interconnects.)
Specifies the number of address ranges.
Base Address 0-15.
High Address 0-15.
DS803 September 21, 2010
www.xilinx.com
7
Product Specification