DS803 Datasheet, PDF (2/8 Pages) Xilinx, Inc – Modeled as a bus bridge in EDK

X-Ref Target - Figure 1
LogiCORE™ IP AXI to AXI Connector (v1.00.a)
mb_0
M_AXI_IP
M_AXI_DP
M_AXI_IC
M_AXI_DC
AXI_Interconnect_0
AXI_Interconnect_2
slave_2
slave_1
axi2axi_connector
AXI_Interconnect_1
slave_3
X12036
Figure 1: System using axi2axi_connector to Cascade Two AXI Interconnects
Application Details
When using an axi2axi_connector (to cascade two AXI Interconnects), the EDK tools set the data width and clock
frequency parameters on the axi2axi_connector IP so that the characteristics of the master and slave interfaces
match.
Also, the EDK tools auto-connect the clock port of the axi2axi_connector so that the interfaces of the connected
interconnect modules are synchronized by the same clock source. Assuming the first interconnect
(AXI_Interconnect0) is connected to the second interconnect (AXI_Interconnect1) using an axi2axi_connector, this is
done based on the following rules:
1. If the native internal data width (C_INTERCONNECT_DATA_WIDTH) of AXI_Interconnect0 is equal to the native
data width of AXI_Interconnect1, then:
a. Set the data width of the axi2axi_connector module (both master and slave interfaces) to the native data
width of the two interconnects.
b. Connect the clock port of the axi2axi_connector to the native clock port (INTERCONNECT_ACLK) of
AXI_Interconnect0 or AXI_Interconnect1, whichever has the lower frequency.
2. If the native internal data widths of AXI_Interconnect0 and AXI_Interconnect1 are not equal, then:
a. Set the data width of the axi2axi_connector module (both interfaces) to match the interconnect which has
smaller native data width.
b. Connect the clock port of the axi2axi_connector to the native clock port of AXI_Interconnect0 or
AXI_Interconnect1, whichever has the smaller native data width. This ensures that clock conversion is
always performed in the wider interconnect so that data bandwidth is never reduced needlessly.
The axi2axi_connector contains slave and master interface I/O signals.
DS803 September 21, 2010
www.xilinx.com
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Product Specification