DS803 Datasheet, PDF (6/8 Pages) Xilinx, Inc – Modeled as a bus bridge in EDK

LogiCORE™ IP AXI to AXI Connector (v1.00.a)
Table 3: I/O Master Signals (Cont’d)
Signal Name
Interface
M_AXI_ARLOCK
AR
M_AXI_ARCACHE [3:0]
AR
M_AXI_ARPROT [2:0]
AR
M_AXI_ARREGION [3:0]
AR
M_AXI_ARQOS [3:0]
AR
M_AXI_ARUSER [C_S_AXI_ARUSER_WIDTH-1:0]
AR
M_AXI_ARVALID
AR
M_AXI_ARREADY
AR
AXI Read Data Channel Signals (R)
M_AXI_RID [C_S_AXI_ID_WIDTH-1:0]
R
M_AXI_RDATA [C_S_AXI_DATA_WIDTH-1:0]
R
M_AXI_RRESP [1:0]
R
M_AXI_RLAST
R
M_AXI_RUSER [C_S_AXI_RUSER_WIDTH-1:0]
R
M_AXI_RVALID
R
M_AXI_RREADY
R
Signal
Type
O
O
O
O
O
O
O
I
I
I
I
I
I
I
O
Description
AXI Read address lock signal.
AXI Read address cache control signal.
AXI Read address protection signal.
Channel address region index.
AR Channel Quality of Service (QoS).
User-defined AR Channel signals.
AXI Read address valid.
AXI Read address ready.
AXI Read data response ID.
AXI Read data.
AXI Read response code.
AXI Read data last signal.
User-defined Channel Signals.
AXI Read valid.
Read ready.
Design Parameters
Table 4 contains the user-visible design parameters for the axi2axi_connector.
Table 4: Design Parameters
Parameter Name
C_S_AXI_PROTOCOL
C_S_AXI_ADDR_WIDTH
C_S_AXI_DATA_WIDTH
C_S_AXI_ID_WIDTH
Default
Value
AXI4
32
N/A
N/A
Allowable
Values
Description
String
(AXI3, AXI4,
AXI4LITE)
Protocol conversion to be performed in
MI of upstream interconnect. (No
conversion if “AXI4”.) Same value is
observed by SI of downstream
interconnect.
constant
(32)
Width of ADDR signals (both S and M
interfaces).
Integer
(32, 64, 128, 256)
Specifies data-width conversions to be
performed in MI of upstream
interconnect or SI of downstream
interconnect, if different than
C_INTERCONNECT_DATA_WIDTH for
each interconnect. Set by tools to match
C_INTERCONNECT_DATA_WIDTH of
either the upstream or downstream
interconnect. (See “Application Details,
page 2.) User cannot override. (Same
value is observed by both
interconnects.)
Integer
Width of all ID signals. Set by tools
based on ID width of upstream
interconnect. (User cannot override.)
DS803 September 21, 2010
www.xilinx.com
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Product Specification