DS803 Datasheet, PDF (3/8 Pages) Xilinx, Inc – Modeled as a bus bridge in EDK

LogiCORE™ IP AXI to AXI Connector (v1.00.a)
I/O Signals
The axi2axi_connector contains one AXI slave interface and one AXI master interface. Each AXI interface contains
a super-set of signals supporting AXI4, AXI3, and AXI4-Lite protocols.
Table 1 provides the global I/O signals.
Global I/O Signals
Table 1: Global I/O Signals
Signal Name
Global Signals
ACLK
ARESETN
Interface
Signal
Type
Description
Global
Global
I
AXI bus clock. Used only to establish clock connectivity to
connected AXI Interconnect interfaces.
I
AXI active-Low reset. (Not used by axi2axi_connector.)
Slave I/O Signals
Table 2 provides the axi2axi_connector I/O slave signals.
Table 2: I/O Slave Signals
Signal Name
Interface
AXI Write Address Channel Signals (AW)
S_AXI_AWID [C_S_AXI_ID_WIDTH-1:0]
AW
S_AXI_AWADDR
[C_S_AXI_ADDR_WIDTH-1:0]
AW
S_AXI_AWLEN [7:0]
AW
S_AXI_AWSIZE [2:0]
AW
S_AXI_AWBURST [1:0]
AW
S_AXI_AWLOCK
AW
S_AXI_AWCACHE [3:0]
AW
S_AXI_AWPROT [2:0]
AW
S_AXI_AWREGION [3:0]
AW
S_AXI_AWQOS [3:0]
AW
S_AXI_AWUSER
[C_S_AXI_AWUSER_WIDTH-1:0]
AW
S_AXI_AWVALID
AW
S_AXI_AWREADY
AW
AXI Write Data Channel Signals (W)
S_AXI_WID [C_S_AXI_ID_WIDTH-1:0]
W
S_AXI_WDATA [C_S_AXI_DATA_WIDTH-1:0]
W
S_AXI_WSTRB [C_S_AXI_DATA_WIDTH/8-1:0]
W
S_AXI_WLAST
W
Signal
Type
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
Description
AXI address Write ID.
AXI Write address.
AXI address Write burst length.
AXI address Write burst size.
AXI address Write burst type.
AXI Write address lock signal.
AXI Write address cache control signal.
AXI Write address protection signal.
Channel address region index
Channel Quality of Service (QoS).
User-defined AW Channel signals.
AXI Write address valid.
AXI Write address ready.
AXI3 Write ID.
AXI Write data.
AXI Write data strobes.
AXI Write data last signal. Indicates the last transfer in a Write
burst.
DS803 September 21, 2010
www.xilinx.com
3
Product Specification