DS803 Datasheet, PDF (4/8 Pages) Xilinx, Inc – Modeled as a bus bridge in EDK

LogiCORE™ IP AXI to AXI Connector (v1.00.a)
Table 2: I/O Slave Signals (Cont’d)
Signal Name
Interface
S_AXI_WUSER
[C_S_AXI_WUSER_WIDTH-1:0]
W
S_AXI_WVALID
W
S_AXI_WREADY
W
AXI Write Response Channel Signals (B)
S_AXI_BID [C_S_AXI_ID_WIDTH-1:0]
B
S_AXI_BRESP [1:0]
B
S_AXI_BUSER
B
S_AXI_BVALID
B
S_AXI_BREADY
B
AXI Read Address Channel Signals (AR)
S_AXI_ARID [C_S_AXI_ID_WIDTH-1:0]
AR
S_AXI_ARADDR
[C_S_AXI_ADDR_WIDTH-1:0]
AR
S_AXI_ARLEN [7:0]
AR
S_AXI_ARSIZE [2:0]
AR
S_AXI_ARBURST [1:0]
AR
S_AXI_ARLOCK
AR
S_AXI_ARCACHE [3:0]
AR
S_AXI_ARPROT [2:0]
AR
S_AXI_ARREGION [3:0]
AR
S_AXI_ARQOS [3:0]
AR
S_AXI_ARUSER
[C_S_AXI_ARUSER_WIDTH-1:0]
AR
S_AXI_ARVALID
AR
S_AXI_ARREADY
AR
AXI Read Data Channel Signals (R)
S_AXI_RID [C_S_AXI_ID_WIDTH-1:0]
R
S_AXI_RDATA [C_S_AXI_DATA_WIDTH-1:0]
R
S_AXI_RRESP [1:0]
R
S_AXI_RLAST
R
S_AXI_RUSER [C_S_AXI_RUSER_WIDTH-1:0]
R
S_AXI_RVALID
R
S_AXI_RREADY
R
Signal
Type
I
I
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
I
Description
User-defined W Channel signals.
AXI Write data valid.
AXI Write data ready.
AXI Write response ID.
AXI Write response code.
User-defined B channel signals.
AXI Write response valid.
Write response ready.
AXI address Read ID.
AXI Read address.
AXI address Read burst length.
AXI address Read burst size.
AXI address Read burst type.
AXI Read address lock signal.
AXI Read address cache control signal.
AXI Read address protection signal.
Channel address region index.
Channel Quality of Service.
User-defined AR Channel signals.
AXI Read address valid.
AXI Read address ready.
AXI Read data response ID.
AXI Read data.
AXI Read response code.
AXI Read data last signal.
User-defined R Channel signals.
AXI Read valid.
Read ready.
DS803 September 21, 2010
www.xilinx.com
4
Product Specification