DS803 Datasheet, PDF (5/8 Pages) Xilinx, Inc – Modeled as a bus bridge in EDK

LogiCORE™ IP AXI to AXI Connector (v1.00.a)
Master I/O Signals
Table 3 contains the axi2axi_connector master I/O signals.
Table 3: I/O Master Signals
Signal Name
AXI Write Address Channel Signals (AW)
M_AXI_AWID [C_S_AXI_ID_WIDTH-1:0]
M_AXI_AWADDR [C_S_AXI_ADDR_WIDTH-1:0]
M_AXI_AWLEN [7:0]
M_AXI_AWSIZE [2:0]
M_AXI_AWBURST [1:0]
M_AXI_AWLOCK
M_AXI_AWCACHE [3:0]
M_AXI_AWPROT [2:0]
M_AXI_AWREGION [3:0]
M_AXI_AWQOS [3:0]
M_AXI_AWUSER
[C_S_AXI_AWUSER_WIDTH-1:0]
M_AXI_AWVALID
M_AXI_AWREADY
AXI Write Data Channel Signals (W)
M_AXI_WID [C_S_AXI_ID_WIDTH-1:0]
M_AXI_WUSER [C_S_AXI_WUSER_WIDTH-1:0]
M_AXI_WDATA C_S_AXI_DATA_WIDTH-1:0]
M_AXI_WSTRB [C_S_AXI_DATA_ WIDTH/8-1:0]
M_AXI_WLAST
M_AXI_WVALID
M_AXI_WREADY
AXI Write Response Channel Signals (B)
M_AXI_BID [C_S_AXI_ID_WIDTH-1:0]
M_AXI_BRESP [1:0]
M_AXI_BUSER [C_S_AXI_BUSER_WIDTH-1:0]
M_AXI_BVALID
M_AXI_BREADY
AXI Read Address Channel Signals (AR)
M_AXI_ARID [C_S_AXI_ID_WIDTH-1:0]
M_AXI_ARADDR
[C_S_AXI_ADDR_WIDTH-1:0]
M_AXI_ARLEN [7:0]
M_AXI_ARSIZE [2:0]
M_AXI_ARBURST [1:0]
Interface
Signal
Type
Description
AW
O
AXI address Write ID.
AW
O
AXI Write address.
AW
O
AXI address Write burst length.
AW
O
AXI address Write burst size.
AW
O
AXI address Write burst type.
AW
O
AXI Write address lock signal.
AW
O
AXI Write address cache control signal.
AW
O
AXI Write address protection signal.
AW
O
Write Address Channel address region index.
AW
O
Write Address Channel Quality of Service (QoS).
AW
O
User-defined AW Channel signals.
AW
O
AXI Write address valid.
AW
I
AXI Write address ready.
W
O
AXI3 Write ID.
W
O
User-defined W Channel signals.
W
O
AXI Write data.
W
O
AXI Write data strobes.
W
O
AXI Write data last signal.
W
O
AXI Write data valid.
W
I
AXI Write data ready.
B
I
AXI Write data response ID.
B
I
AXI Write response code.
B
I
User-defined B Channel signals.
B
I
AXI Write response valid.
B
O
Write response ready.
AR
O
AXI address Read ID.
AR
O
AXI Read address.
AR
O
AXI address Read burst length.
AR
O
AXI address Read burst size.
AR
O
AXI address Read burst type.
DS803 September 21, 2010
www.xilinx.com
5
Product Specification