DS650 Datasheet, PDF (8/9 Pages) Xilinx, Inc – Agilent Trace Core 2

Agilent Trace Core 2 (ATC2) (v1.04a)
Performance and Resource Utilization
The configuration number and associated device is shown in Table 4.
Table 4: Configuration Details
Configuration Number
Device
Description
Config1
Xc7v585t-2ffg1157
Signal Bank count - 2, pin count -8
Config2
Xc7v585t-3ffg1157
Signal Bank count - 64, pin count -64
Config3
Xc7v585t-2ffg1157
Signal Bank count - 16, pin count -32
Verification
Xilinx has verified the ATC2 core in a proprietary test environment, using an internally developed bus functional
model.
References
1. More information on the ChipScope Pro software and cores is available in the Software and Cores User Guide,
located at http://www.xilinx.com/documentation.
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE^® Design Suite Embedded
Edition software under the terms of the Xilinx End User License. The core is generated using the Xilinx ISE
Embedded Edition software (EDK).
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page.
For information on pricing and availability of other Xilinx LogiCORE modules and software, please contact your
local Xilinx sales representative.
DS650 June 22, 2011
www.xilinx.com
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Product Specification