DS650 Datasheet, PDF (2/9 Pages) Xilinx, Inc – Agilent Trace Core 2

Agilent Trace Core 2 (ATC2) (v1.04a)
Applications
The ATC2 core is designed to be used in any application that requires verification or debugging using the Chip-
Scope Pro software and an external Agilent Logic Analyzer.
Functional Description
Communication with the ATC2 core is conducted using a connection to the JTAG port via the ICON core, as shown
in Figure 1.
X-Ref Target - Figure 1
ChipScope Pro
ICON Core
ChipScope Pro
ATC2 Core
CONTROL0
CONTROL
CLK
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DS650_01_121007
Figure 1: ATC2 Core Connection to ICON Core
The data path of the ATC2 core consists of:
 Up to 64 run-time selectable input signal banks that connect to the user’s FPGA design.
 Up to 128 output data pins that connect to an Agilent logic analyzer’s probe connectors.
 Optional 2x time-division multiplexing (TDM) available on each output data pin that can be used to double
the width of each individual signal bank from 128 to 256 bits.
 Supports both asynchronous timing and synchronous state capture modes.
 Supports any valid I/O standard, drive strength, and output slew rate on each output data pin on an
individual pin-by-pin basis.
 Supports any Agilent Technologies probe connection technology.
The maximum number of data probe points available at run time is calculated as:
(64 data ports) * (128 bits per data port) * (2x TDM) = 16,384 probe points.
DS650 June 22, 2011
www.xilinx.com
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Product Specification