DS650 Datasheet, PDF (4/9 Pages) Xilinx, Inc – Agilent Trace Core 2

Agilent Trace Core 2 (ATC2) (v1.04a)
TDM Rate
The ATC2 core does not use on-chip memory resources to store the captured trace data. Instead, it transmits the data
to be captured by an Agilent logic analyzer that is attached to the FPGA pins using a special probe connector. The
data can be transmitted out the device pins at the same rate as the incoming DATA port (TDM Rate = 1x) or twice
the rate as the DATA port (TDM Rate = 2x). The TDM rate can be set to "2x" only when the acquisition mode is set
to State - Synchronous Sampling.
ATC2 Core Pin and Signal Parameters
After you have set up the ATC2 core acquisition and state parameters, click Next. This takes you to the screen in the
CORE Generator tool that is used to set up the ATC2 pin and signal parameters.
Enable Auto Setup
The Enable Auto Setup option is used to enable a feature that allows the Agilent Logic Analyzer to automatically set
up the appropriate ATC2 pin to Logic Analyzer pod connections. This feature also allows the Agilent Logic Ana-
lyzer to automatically determine the optimal phase and voltage sampling offsets for each ATC2 pin. This feature is
enabled by default.
Enable Always On Mode
The Enable Always On Mode parameter forces an ATC2 core always to enable its internal logic and output buffers.
The "Always On" mode ensures that signal bank 0 is driven out to the ATD pins upon FPGA device configuration.
This mode makes it possible to capture events that immediately follow device configuration without having to first
set up the ATC2 core manually. This feature is disabled by default and is only available when the acquisition mode
is set to Timing - Asynchronous Sampling mode.
ATD Pin Count
The ATC2 core can implement any number of ATD output pins in the range of 4 through 64.
Driver Endpoint Type
The Driver Endpoint Type setting is used to control whether single-ended or differential output drivers are used on
the ATCK and ATD output pins. All ATCK and ATD pins must use the same driver endpoint type.
Pin Edit Mode
The pin edit mode is a time saving feature that allows you to change the IO Standard, Drive and Slew Rate pin
parameters on individual pins or together as a group of pins. Selecting ATD drivers same as ATCK allows you to
change the ATCK pin parameters and forces all ATD pins to the same settings. Selecting ATD drivers different than
ATCK allows you to edit the parameters of each pin independently from one another. You need to set unique pin
locations for each individual pin regardless of the Pin Edit Mode parameter setting.
Signal Bank Count
The ATC2 core contains an internal, run-time selectable data signal bank multiplexer. The Signal Bank Count setting
is used to denote the number of data input ports or signal banks the multiplexer will implement. The valid Signal
Bank Count values are 1, 2, 4, 8, 16, 32, and 64.
Signal Bank Width
The width of each input signal bank data port of the ATC2 core depends on the capture mode and the TDM rate. In
State mode, the width of each signal bank data port is equal to (ATD pin count) * (TDM rate). In Timing mode, the
DS650 June 22, 2011
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