DS650 Datasheet, PDF (5/9 Pages) Xilinx, Inc – Agilent Trace Core 2

Agilent Trace Core 2 (ATC2) (v1.04a)
width of each signal bank data port is equal to (ATD pin count + 1) * (TDM rate) since the ATCK pin is used as an
extra data pin.
ATC2 Core ATCK and ATD Pin Parameters
After you have set up the ATC2 core pin and signal parameters, click Next. This takes you to the screen in the CORE
Generator tool that is used to set up the ATCK and ATD pin parameters.
The output clock (ATCK) and data (ATD) pins are instantiated inside the ATC2 core for your convenience. This
means that although you do not have to manually bring the ATCK and ATD pins through every level of hierarchy
to the top-level of your design, you do need to specify the location and other characteristics of these pins in the
CORE Generator. These pin attributes are then added to the *.ncf file of the ATC2 core. Using the settings in the Pin
Parameters table, you can control the location, I/O standard, output drive and slew rate of each individual ATCK
and ATD pin.
Pin Name
The ATC2 core has two types of output pins: ATCK and ATD. The ATCK pin is used as a clock pin when the capture
mode is set to State and is used as a data pin when the capture mode is set to Timing. The ATD pins are always used
as data pins. The names of the pins cannot be changed.
Pin Loc
The Pin Loc column is used to set the location of the ATCK or ATD pin.
IO Standard
The IO Standard column is used to set the I/O standard of each individual ATCK or ATD pin. The I/O standards
that are available for selection depend on the device family and driver endpoint type. The names of the I/O stan-
dards are the same as those in the IOSTANDARD section of the Constraints Guide in the Xilinx Software Documen-
tation.
Drive
The Drive column setting denotes the maximum output drive current of the pin driver and ranges from 2 to 24 mA,
depending on the IO Standard selection.
Slew Rate
The Slew Rate column can be set to either FAST or SLOW for each individual ATCK or ATD pin.
Generating the Core
After entering the ATC2 core parameters, click Finish to create the ATC2 core files. While the ATC2 core is being
generated, a progress indicator appears. Depending on the host computer system, it might take several minutes for
the ATC2 core generation to complete. After the ATC2 core has been generated, a list of files that are generated will
appear in a separate Readme File window.
DS650 June 22, 2011
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Product Specification