DS650 Datasheet, PDF (3/9 Pages) Xilinx, Inc – Agilent Trace Core 2

Agilent Trace Core 2 (ATC2) (v1.04a)
Core Data Capture and Run-Time Control
The external Agilent logic analyzer is used to trigger on and capture the data that passes through the ATC2 core.
which allows the user to take full advantage of the complex triggering, deep trace memory, and system-level data
correlation features of the Agilent logic analyzer. In addition, the analyzer provides increased visibility of internal
design nodes provided by the ATC2 core and is also used to control the run-time selection of the active data port by
communicating with the ATC2 core via a JTAG port connection.
CORE Generator
The CORE Generator tool provides the ability to define and generate a customized ATC2 core for adding external
Agilent logic analyzer capture capabilities to the HDL designs. The user can customize the number of pins (and
their characteristics) to be used for external capture as well as how many input data ports are needed. The user can
also customize the type of capture mode (state or timing) to be used as well as the TDM compression mode (1x or
2x).
After the CORE Generator tool validates the parameters you defined, it generates an XST netlist (*.ngc) and other
files specific to the HDL language and synthesis tool associated with the CORE Generator project. The can easily
generate the netlist and code examples for use in normal FPGA design flows.
In the Debug & Verification > ChipScope Pro IP category of the Xilinx CORE Generator tool, select ATC2 (Chip-
Scope Pro - Agilent Trace Core 2) and click the Customize and Generate link in the right side of the window.
ATC2 Core Acquisition and State Parameters
The CORE Generator tool is used to set up the ATC2 core acquisition and state parameters.
Entering the Component Name
The Component Name field can consist of any combination of alpha-numeric characters in addition to the under-
score symbol. However, the underscore symbol cannot be the first character in the component name.
Generating an Example Design
The ATC2 core generator normally generates standard Xilinx CORE Generator output files only, such as netlist and
instantiation template files. If, in addition, you want the Xilinx CORE Generator tool to generate an example design
that uses the ATC2 core, select the Generate Example Design checkbox. The example design contains everything
necessary to implement the design, including source code and implementation script files.
Selecting the Acquisition Mode
The acquisition mode of the ATC2 core can be set to either to Timing - Asynchronous Sampling mode for asynchro-
nous data capture or State - Synchronous Sampling mode for synchronous data capture to the CLK input signal. In
State mode, the data path through the ATC2 core uses pipeline flip-flops that are clocked on the CLK input port sig-
nal. In Timing mode, the data path through the ATC2 core is composed purely of combinational logic all the way to
the output pins. Also, in Timing mode, the ATCK pin is used as an extra data pin.
Max Frequency Range
The Max Frequency Range parameter is used to specify the maximum frequency range in which you expect to oper-
ate the ATC2 core. The implementation of the ATC2 core will be optimized for the maximum frequency range selec-
tion. The valid maximum frequency ranges are 0-100 MHz, 101-200 MHz, 201-300 MHz, and 301-500 MHz. The
maximum frequency range selection only has an affect on core implementation when the acquisition mode is set to
State - Synchronous Sampling.
DS650 June 22, 2011
www.xilinx.com
3
Product Specification