DS650 Datasheet, PDF (6/9 Pages) Xilinx, Inc – Agilent Trace Core 2

Agilent Trace Core 2 (ATC2) (v1.04a)
Using the ATC2 Core
To instantiate the example ATC2 core HDL files into your design, use the following guidelines to connect the ATC2
core port signals to various signals in your design:
• Connect the ATC2 core's CONTROL port signal to an unused control port of the ICON core instance in the
design
• Connect all unused bits of the ATC2 core's asynchronous and synchronous input signals to a "0". This prevents
the mapper from removing the unused trigger and/or data signals and also avoids any DRC errors during the
implementation process
• For best results, make sure the State mode input data port signals are synchronous to the ATC2 clock signal
(CLK); this is not important for Timing mode input data port signals.
Ports and Parameters
Ports
The ATC2 Interface ports are listed and described in Table 1.
Table 1: ATC2 Interface Ports
Port Name
Direction
Description
CLK
IN
Design clock needed to synchronize the data in state mode. Optional (depends on
state_synchronous parameter).
CONTROL[35:0]
INOUT
Control bus to ICON core. Mandatory.
DATA<n>[<m>-1:0]
Data signal input bank number <n> of width <m>. Optional, except for <n> = 0, which
IN
is mandatory (depends on parameter signal_bank_count = <n>+1, where <n> ranges
from 0 through 63).
Parameters
The ATC2 XCO parameters are listed and described in Table 2
Table 2: ATC2 XCO Parameters
Parameter Name
Allowable Values
Default
Value
Description
atck_drive
N/A
N/A
Drive strength for ATCK pin.
atck_io_standard
N/A
N/A
IO standard for ATCK pin.
atck_pin_loc
any alphanumeric
none
Pin location for ATCK pin.
atck_slew_rate
fast, slow
fast
slew rate for ATCK pin.
atd_drivers
same_as_atck,
different_than_atck
same_as_at
ck
Whether to use atck settings for all data pins
(same_as_atck) or individual settings for data pins
(different_than_
atck)
atd_pin_count
4-64
8
Number of data pins to use.
atd<n>_drive
N/A
N/A
Drive strength for data pin <n>.
atd<n>_io_standard
N/A
N/A
IO standard for data pin <n>.
atd<n>_pin_loc
any alphanumeric
none
Pin location for data pin <n>.
atd<n>_slew_rate
fast, slow
fast
slew rate for data pin <n>.
DS650 June 22, 2011
www.xilinx.com
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Product Specification