DS631 Datasheet, PDF (8/9 Pages) Xilinx, Inc – Configurable number of PLB interfaces from 1 to 8

XPS Mutex (v1.00c)
XPS Mutex User Configuration Register (USER)
The USER configuration is used to store a 32-bit value associated with a mutex. It can contain any
arbitrary information. Bit assignment in the USER register is described in Table 8.
Table 7: XPS Mutex User Configuration Register (USER)
USER
0
31
Table 8: XPS Mutex Read Data Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
0 - 31
USER
R/W
-
Description
User configuration register
Design Implementation
Target Technology
The intended target technology is an FPGA in one of the following families: Spartan-3, Spartan-3E,
Spartan-3A, Spartan-3A DSP, Automotive Spartan-3/3A/3E/3A DSP, Virtex-4, Virtex-4QV, Virtex-4Q,
Virtex-5, Virtex-6.
Reference Documents
1. IBM CoreConnect128-Bit Processor Local Bus, Architectural Specification (v4.6).
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Revision History
Date
07/04/07
02/20/08
7/25/08
10/02/08
4/24/09
6/26/09
Version
1.0
1.1
1.2
1.3
1.4
1.5
Revision
Initial Xilinx release.
Updated CPUID information.
Added QPro^® Virtex-4 Hi-Rel and QPro Virtex-4 Rad Tolerant support.
Initial version for v1.00b
Replaced references to supported device families and tool name(s) with hyperlink to
PDF file.
Updated for EDK_L 11.2; created v1.00c.
8
www.xilinx.com
DS631 June 24, 2009
Product Specification