DS631 Datasheet, PDF (3/9 Pages) Xilinx, Inc – Configurable number of PLB interfaces from 1 to 8

XPS Mutex (v1.00c)
Table 1: XPS Mutex PLBv46 I/O Signal Description (Contd)
Port
Signal Name
Interface I/O
Initial
State
P20 PLB<x>_rdBurst
PLB
I
-
P21 PLB<x>_wrPendReq
PLB
I
-
P22 PLB<x>_rdPendReq
PLB
I
-
P23 PLB<x>_wrPendPri[0:1]
PLB
I
-
P24 PLB<x>_rdPendPri[0:1]
PLB
I
-
P25 PLB<x>_reqPri[0:1]
PLB
I
-
P26 PLB<x>_TAttribute[0:15]
PLB
I
-
PLB Slave Interface Signals
P27 Sl<x>_addrAck
PLB
O
0
P28 Sl<x>_SSize[0:1]
PLB
O
0
P29 Sl<x>_wait
PLB
O
0
P30 Sl<x>_rearbitrate
PLB
O
0
P31 Sl<x>_wrDAck
PLB
O
0
P32 Sl<x>_wrComp
PLB
O
0
P33
Sl<x>_rdDBus[0:
C_SPLB_DWIDTH - 1]
PLB
O
0
P34 Sl<x>_rdDAck
PLB
O
0
P35 Sl<x>_rdComp
PLB
O
0
P36
Sl<x>_MBusy[0:
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
P37
Sl<x>_MWrErr[0:
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
P38
Sl<x>_MRdErr[0:
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Unused PLB Slave Interface Signals
P39 Sl<x>_wrBTerm
PLB
O
0
P40 Sl<x>_rdWdAddr[0:3]
PLB
O
0
P41 Sl<x>_rdBTerm
PLB
O
0
P42
Sl<x>_MIRQ[0:
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Description
PLB burst read transfer
PLB pending bus write request
PLB pending bus read request
PLB pending write request
priority
PLB pending read request
priority
PLB current request priority
PLB transfer attribute
Slave address acknowledge
Slave data bus size
Slave wait
Slave bus rearbitrate
Slave write data acknowledge
Slave write transfer complete
Slave read data bus
Slave read data acknowledge
Slave read transfer complete
Slave busy
Slave write error
Slave read error
Slave terminate write burst
transfer
Slave read word address
Slave terminate read burst
transfer
Master interrupt request
DS631 June 24, 2009
www.xilinx.com
3
Product Specification