DS631 Datasheet, PDF (4/9 Pages) Xilinx, Inc – Configurable number of PLB interfaces from 1 to 8

XPS Mutex (v1.00c)
XPS Mutex Design Parameters
The XPS Mutex design is parameterized to tailor it for different systems. This allows the user to
configure a design that utilizes the resources required by the system only and that operates with the
best possible performance. The features that can be parameterized in the XPS Mutex design are shown
in Table 2. The PLB related generics, G2 through G9, are separately configured for each interface.
Table 2: XPS Mutex Design Parameters
Generic Feature/Description Parameter Name
Allowable Values
Default
Value
VHDL
Type
System Parameter
G1
Target FPGA family
C_FAMILY
spartan3, aspartan3,
spartan3e,
aspartan3e,
spartan3a,
aspartan3a,
spartan3adsp,
aspartan3adsp,
spartan6, virtex4,
qrvirtex4, qvirtex4,
virtex5, virtex6
virtex-5
string
PLB Parameters
G2
PLB Base Address
C_SPLB<x>_BASE
ADDR
Valid Address^[1]
None^[3]
std_logic_
vector
G3
PLB High Address
C_SPLB<x>_HIGHA
DDR
Valid Address^[2]
None^[3]
std_logic_
vector
G4
PLB least significant
address bus width
C_SPLB<x>_AWIDT
H
32
32
integer
G5
PLB data width
C_SPLB<x>_DWIDT
H
32, 64, 128
32
integer
0 = Shared Bus
G6
Selects point-to-point or
shared bus topology
C_SPLB<x>_P2P
Topology
1 = Point-to-Point Bus
0
integer
Topology^[4]
G7
PLB Master ID Bus Width
C_SPLB<x>_MID_
WIDTH
log₂(C_SPLB_NUM_
MASTERS) with a
minimum value of 1
1
integer
G8
Number of PLB Masters
C_SPLB<x>_NUM_
MASTERS
1 - 16
1
integer
G9
Support Bursts
C_SPLB<x>_SUPP
ORT_BURSTS
0
0
integer
G10
Width of the Slave Data C_SPLB_NATIVE_
Bus
DWIDTH
32
32
integer
XPS Mutex Parameters
Specify if PLB interfaces
G11 are synchronous or
C_ASYNC_CLKS
asynchronous
0-1
0
Integer
4
www.xilinx.com
DS631 June 24, 2009
Product Specification