DS631 Datasheet, PDF (6/9 Pages) Xilinx, Inc – Configurable number of PLB interfaces from 1 to 8

XPS Mutex (v1.00c)
Table 3: XPS Mutex Parameter-Port Dependencies (Contd)
Generic
or Port
Name
Affects Depends Relationship Description
I/O Signals
P5
PLB<x>_masterID[0:
C_SPLB_MID_WIDTH - 1]
Width of the PLB<x>_masterID
-
G7
varies according to
C_SPLB<x>_MID_WIDTH
P7
PLB<x>_BE[0:
(C_SPLB_DWIDTH/8) -1]
-
G5
Width of the PLB<x>_BE varies
according to C_SPLB<x>_DWIDTH
P10
PLB<x>_wrDBus[0:
C_SPLB_DWIDTH - 1]
Width of the PLB<x>_wrDBus
-
G5
varies according to
C_SPLB<x>_DWIDTH
P33
Sl<x>_rdDBus[0:
C_SPLB_DWIDTH - 1]
-
G5
Width of the Sl<x>_rdDBus varies
according to C_SPLB<x>_DWIDTH
P36
Sl<x>_MBusy[0:
C_SPLB_NUM_MASTERS - 1]
-
Width of the Sl<x>_MBusy varies
G8
according to
C_SPLB<x>_NUM_MASTERS
P37
Sl<x>_MWrErr[0:
C_SPLB_NUM_MASTERS - 1]
-
Width of the Sl<x>_MWrErr varies
G8
according to
C_SPLB<x>_NUM_MASTERS
P38
Sl<x>_MRdErr[0:
C_SPLB_NUM_MASTERS - 1]
-
Width of the Sl<x>_MRdErr varies
G8
according to
C_SPLB<x>_NUM_MASTERS
P42
Sl<x>_MIRQ[0:
C_SPLB_NUM_MASTERS - 1]
-
Width of the Sl<x>_MIRQ varies
G8
according to
C_SPLB<x>_NUM_MASTERS
XPS Mutex Register Descriptions
Each interface of the XPS Mutex core can access all mutexes. Only one interface at the time can access
any of the mutexes, i.e. all other PLB interfaces are blocked while one is accessing any of the mutexes.
PLB interface arbitration has fixed priority where PLB0 has the highest priority and PLB7 the lowest.
Table 4 shows all the XPS Mutex registers and their addresses offsets.
Table 4: XPS Mutex Registers
Base Address +
Offset (hex)
Register Name
C_BASEADDR + 0x0 MUTEX
C_BASEADDR + 0x4 USER
C_BASEADDR + 0x8 to Reserved
0xFC
Access Default
Type Value (hex)
Description
R/W
0
Mutex register for mutex ownership
N/A
0
USER configuration register.
Reserved for future use
XPS Mutex Register (MUTEX)
The MUTEX register contains one mandatory and two optional bit fields. The LOCK bit is required
since this bit determines if the mutex is in locked or released state. CPUID is usually included to control
access of who may manipulate the mutex. It is only the owner of the mutex that may release it. For extra
safety an optional HWID field is also available. The HWID bits are not accessible by the user and are
handled implicitly in the background. HWID contains the PLB master ID and on which port the PLB
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DS631 June 24, 2009
Product Specification