DS631 Datasheet, PDF (1/9 Pages) Xilinx, Inc – Configurable number of PLB interfaces from 1 to 8

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XPS Mutex (v1.00c)
DS631 June 24, 2009
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Product Specification
Introduction
In a multi processor environment, the processors share
common resources. The mutex provides a mechanism
for mutual exclusion to enable one process to gain
exclusive access to a particular resource.
XPS Mutex core contains a configurable number of
mutexes. Each of these can be associated with a 32-bit
User configuration register to store arbitrary data.
Features
• PLB interface is based on PLB v4.6 specification
• Configurable number of PLB interfaces from 1 to 8
• Configurable asynchronous or synchronous
interface operation
• Configurable USER register
• Configurable number of mutexes
• Configurable CPUID width
• Configurable enhanced security through hardware
identification support
LogiCORE™ Facts
Core Specifics
Supported Device
Family
Spartan^®-3, Spartan-3E,
Spartan-6, Spartan-3A/3A
DSP/3AN, Automotive
Spartan-3/3A/3A DSP/ 3E,
Virtex^®-4, Virtex-4Q, Virtex-4QV,
Virtex-5, Virtex-6
Version of core
xps_mutex
Resources Used¹
v1.00c
Min
Max
Slices
110
560
LUTs
115
460
FFs
125
730
Block RAMs
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Special Features
None
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation
Template
N/A
Design Tool Requirements
Xilinx Implementation
Tools
ISE® 11.1 or later
Verification
N/A
Simulation
ModelSim PE/SE 6.4b or later
Synthesis
XST
Support
Provided by Xilinx, Inc.
1. Resources for Virtex-4 implementation with 16 mutexes and 8 bits
CPUID. Minimum has one and maximum eight PLB interface
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DS631 June 24, 2009
www.xilinx.com
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Product Specification