DS631 Datasheet, PDF (2/9 Pages) Xilinx, Inc – Configurable number of PLB interfaces from 1 to 8

XPS Mutex (v1.00c)
Functional Description
The XPS Mutex core contains a configurable number of mutexes. Each of these can be associated with
a 32-bit user configuration register to store arbitrary data.
In a multi processor environment, the processors share common resources. The mutex provides a
mechanism for mutual exclusion to enable one process to gain exclusive access to a particular resource.
XPS Mutex I/O Signals
The XPS Mutex has a configurable number of PLB interfaces that are used to connect it to the rest of the
system. All PLB interfaces can be independently configured and contain the signals listed in Table 1
where <x> denotes the interface number (0 to 7).
Table 1: XPS Mutex PLBv46 I/O Signal Description
Port
Signal Name
Interface I/O
Initial
State
Description
System Signals
P1 SPLB<x>_Clk
System
I
-
PLB clock
P2 SPLB<x>_Rst
System
I
-
PLB reset, active high
PLB Interface Signals
P3 PLB<x>_ABus[0:31]
PLB
I
-
PLB address bus
P4 PLB<x>_PAValid
PLB
I
-
PLB primary address valid
P5
PLB<x>_masterID[0:
C_SPLB_MID_WIDTH - 1]
PLB
I
-
PLB current master identifier
P6 PLB<x>_RNW
PLB
I
-
PLB read not write
P7
PLB<x>_BE[0:
(C_SPLB_DWIDTH/8) - 1]
PLB
I
-
PLB byte enables
P8 PLB<x>_size[0:3]
PLB
I
-
PLB size of requested transfer
P9 PLB<x>_type[0:2]
PLB
I
-
PLB transfer type
P10
PLB<x>_wrDBus[0:
C_SPLB_DWIDTH - 1]
PLB
I
-
PLB write data bus
Unused PLB Interface Signals
P11 PLB<x>_UABus[0:31]
PLB
I
-
PLB upper address bits
P12 PLB<x>_SAValid
PLB
I
-
PLB secondary address valid
P13 PLB<x>_rdPrim
PLB
I
-
PLB secondary to primary read
request indicator
P14 PLB<x>_wrPrim
PLB
I
-
PLB secondary to primary write
request indicator
P15 PLB<x>_abort
PLB
I
-
PLB abort bus request
P16 PLB<x>_busLock
PLB
I
-
PLB bus lock
P17 PLB<x>_MSize[0:1]
PLB
I
-
PLB data bus width indicator
P18 PLB<x>_lockErr
PLB
I
-
PLB lock error
P19 PLB<x>_wrBurst
PLB
I
-
PLB burst write transfer
2
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DS631 June 24, 2009
Product Specification