DS631 Datasheet, PDF (7/9 Pages) Xilinx, Inc – Configurable number of PLB interfaces from 1 to 8

XPS Mutex (v1.00c)
master is attached. This guarantees that no other processor can fake the CPUID and gain access over the
mutex. Bit assignment in the MUTEX register is described in Table 6.
CPUID is a unique identification value assigned by the tools to software that executes on each
processor. Since CPUID is only assigned to software created from within EDK, any other master that
accesses the mutex must be manually assigned a unique number that does not interfere with the others.
Examples of this are external processors and hardware IPs other than MicroBlaze™ and PowerPC^®
processors. Each processor has its allocated CPUID listed in xparameters.h.
Mutex lock and release process
The steps needed to lock and release a mutex (for a free mutex the MUTEX register is zero):
• Write <CPUID & 1> to the MUTEX register. If the mutex is free the lock bit will be set to one and the
CPUID field will be update with the new CPUID. If C_ENABLE_HW_PROT is enabled, the
PLB_masterID and interface number is also stored for enhanced protection. Should the mutex
already be locked the access is ignored.
• Read back the MUTEX register to verify that the mutex has been locked by the current CPU by
comparing the value with the written CPUID, if not retry step 1 until ownership has been granted.
• Manipulate the shared resource that is protected by the mutex.
• Release mutex by writing <CPUID & 0> to the mutex register. If C_ENABLE_HW_PROT is
enabled, the PLB_masterID and interface number are also taken into account. The mutex will
automatically set the MUTEX register to zero.
If the "wrong" processor tries to free the mutex with C_ENABLE_HW_PROT active with the correct
CPUID the operation will be ignored since both the HWID and CPUID must match for the operation to
be successful. Also, the operation is ignored if the "right" processor writes the wrong CPUID.
Table 5: XPS Mutex Write Data Register
Reserved
0
CPUID
22
23
30
Lock
31
Table 6: XPS Mutex Write Data Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
0 - 22
Reserved
N/A
0
23 - 30
CPUID
R/W
-
31
LOCK
R/W
-
Description
Reserved for future use.
Unique processor ID number.
Lock status: 0 = free, 1 = Mutex currently
owned by CPUID.
DS631 June 24, 2009
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Product Specification