XA2C32A Datasheet, PDF (7/14 Pages) Xilinx, Inc – AEC-Q100 device qualification and full PPAP support

R
Internal Timing Parameters
Symbol
Parameter⁽¹⁾
Buffer Delays
T_IN
T_DIN
T_GCK
T_GSR
T_GTS
T_OUT
T_EN
P-term Delays
Input buffer delay
Direct register input delay
Global Clock buffer delay
Global set/reset buffer delay
Global 3-state buffer delay
Output buffer delay
Output buffer enable/disable delay
T_CT
T_LOGI1
T_LOGI2
Macrocell Delay
Control term delay
Single p-term delay adder
Multiple p-term delay adder
T_PDI
Input to output valid
T_LDI
Setup before clock (transparent latch)
T_SUI
Setup before clock
T_HI
Hold after clock
T_ECSU
Enable clock setup time
T_ECHO
Enable clock hold time
T_COI
Clock to output valid
T_AOI
Set/reset to output valid
Feedback Delays
T_F
Feedback delay
T_OEM
Macrocell to global OE delay
I/O Standard Time Adder Delays 1.5V CMOS
T_HYS15
Hysteresis input adder
T_OUT15
Output adder
T_SLEW15
Output slew rate adder
I/O Standard Time Adder Delays 1.8V CMOS
T_HYS18
T_OUT18
T_SLEW
Hysteresis input adder
Output adder
Output slew rate adder
XA2C32A CoolRunner-II Automotive CPLD
-6
Min.
Max.
-
1.7
-
2.4
-
2.0
-
2.0
-
2.1
-
2.0
-
3.4
-
1.6
-
1.1
-
0.5
-
0.7
-
2.5
1.8
-
0.0
-
1.7
-
0.0
-
-
0.7
-
1.5
-
1.4
-
0.8
-
4.0
-
1.0
-
5.0
-
4.0
-
0.0
-
5.0
-7
Min.
Max.
-
1.7
-
2.4
-
2.0
-
2.0
-
1.5
-
2.0
-
4.7
-
1.6
-
1.1
-
0.5
-
0.7
-
2.5
1.8
-
0.0
-
1.7
-
0.0
-
-
0.7
-
1.5
-
1.4
-
0.2
4.2
1.0
5.0
4.0
0.0
5.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS552 (v1.1) May 5, 2007
www.xilinx.com
7
Product Specification