XA2C32A Datasheet, PDF (12/14 Pages) Xilinx, Inc – AEC-Q100 device qualification and full PPAP support

XA2C32A CoolRunner-II Automotive CPLD
R
I/O⁽²⁾
1
I/O 2
I/O 3
GND 4
I/O 5
VQG44
I/O 6
V_CCIO1
7
I/O 8
Top View
TDI 9
TMS ¹⁰
TCK ¹¹
33
I/O⁽¹⁾
32
I/O⁽¹⁾
31
I/O⁽¹⁾
30
I/O⁽³⁾
29
I/O
28
I/O
27
I/O
26
V_CCIO2
25
GND
24 TDO
23 I/O
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
Figure 6: VQ44 Package
CoolRunner-II Automotive Requirements and Recommendations
Requirements
The following requirements are for all automotive applica-
tions:
1. Use a monotonic, fast ramp power supply to power up
CoolRunner-II . A V_CC ramp time of less than 1 ms is
required.
2. Do not float I/O pins during device operation. Floating
I/O pins can increase I_CC as input buffers will draw
1-2 mA per floating input. In addition, when I/O pins are
floated, noise can propagate to the center of the CPLD.
I/O pins should be appropriately terminated with
bus-hold or pull-up. Unused I/Os can also be configured
as C_GND (programmable GND).
3. Do not drive I/O pins without V_CC/V_CCIO powered.
4. Sink current when driving LEDs. Because all Xilinx
CPLDs have N-channel pull-down transistors on
outputs, it is required that an LED anode is sourced
through a resistor externally to V_CC. Consequently, this
will give the brightest solution.
5. Avoid pull-down resistors. Always use external pull-up
resistors if external termination is required. This is
because the CoolRunner-II Automotive CPLD, which
includes some I/O driving circuits beyond the input and
output buffers, may have contention with external
pull-down resistors, and, consequently, the I/O will not
switch as expected.
6. Do not drive I/Os pins above the V_CCIO assigned to its
I/O bank.
a. The current flow can go into V_CCIO and affect a user
voltage regulator.
b. It can also increase undesired leakage current
associated with the device.
c. If done for too long, it can reduce the life of the
device.
7. Do not rely on the I/O states before the CPLD
configures. During power up, the CPLD I/Os may be
affected by internal or external signals.
8. Use a voltage regulator which can provide sufficient
current during device power up. As a rule of thumb, the
regulator needs to provide at least three times the peak
current while powering up a CPLD in order to guarantee
the CPLD can configure successfully.
9. Ensure external JTAG terminations for TMS, TCK, TDI,
TDO should comply with the IEEE 1149.1. All Xilinx
CPLDs have internal weak pull-ups on TDI, TMS, and
TCK.
12
www.xilinx.com
DS552 (v1.1) May 5, 2007
Product Specification