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XA2C32A Datasheet, PDF (5/14 Pages) Xilinx, Inc – AEC-Q100 device qualification and full PPAP support
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XA2C32A CoolRunner-II Automotive CPLD
LVCMOS 1.8V DC Voltage Specifications
Symbol
VCCIO
VIH
VIL
VOH
VOL
Parameter
Input source voltage
High level input voltage
Low level input voltage
High level output voltage,
Industrial grade
High level output voltage, Q-grade
Low level output voltage, Industrial
grade
Low level output voltage, Q-grade
Test Conditions
IOH = –8 mA, VCCIO = 1.7V
IOH = –0.1 mA, VCCIO = 1.7V
IOH = –4 mA, VCCIO = 1.7V
IOH = –0.1 mA, VCCIO = 1.7V
IOL = 8 mA, VCCIO = 1.7V
IOL = 0.1 mA, VCCIO = 1.7V
IOL = 4 mA, VCCIO = 1.7V
IOL = 0.1 mA, VCCIO = 1.7V
Min.
1.7
0.65 x VCCIO
–0.3
VCCIO – 0.45
VCCIO – 0.2
VCCIO – 0.45
VCCIO – 0.2
-
-
-
-
Max.
1.9
VCCIO + 0.3(1)
0.35 x VCCIO
-
-
-
-
0.45
0.2
0.45
0.2
Units
V
V
V
V
V
V
V
V
V
V
V
1. The VIH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II input buffer can tolerate up
to 3.9V without physical damage.
LVCMOS 1.5V DC Voltage Specifications(1)
Symbol
VCCIO
VT+
VT-
VOH
Parameter
Input source voltage
Input hysteresis threshold voltage
High level output voltage,
Industrial grade
High level output voltage, Q-grade
VOL
Low level output voltage, Industrial
grade
Low level output voltage, Q-grade
Notes:
1. Hysteresis used on 1.5V inputs.
Test Conditions
IOH = –8 mA, VCCIO = 1.4V
IOH = –0.1 mA, VCCIO = 1.4V
IOH = –4 mA, VCCIO = 1.4V
IOH = –0.1 mA, VCCIO = 1.4V
IOL = 8 mA, VCCIO = 1.4V
IOL = 0.1 mA, VCCIO = 1.4V
IOL = 4 mA, VCCIO = 1.4V
IOL = 0.1 mA, VCCIO = 1.4V
Min.
1.4
0.5 x VCCIO
0.2 x VCCIO
VCCIO – 0.45
VCCIO – 0.2
VCCIO – 0.45
VCCIO – 0.2
-
-
-
-
Max.
1.6
0.8 x VCCIO
0.5 x VCCIO
-
-
-
-
0.4
0.2
0.4
0.2
Units
V
V
V
V
V
V
V
V
V
V
V
Schmitt Trigger Input DC Voltage Specifications
Symbol
VCCIO
VT+
VT-
Parameter
Input source voltage
Input hysteresis threshold voltage
Test Conditions
Min.
1.4
0.5 x VCCIO
0.2 x VCCIO
Max.
3.9
0.8 x VCCIO
0.5 x VCCIO
Units
V
V
V
AC Electrical Characteristics Over Recommended Operating Conditions
Symbol
TPD1
TPD2
TSUD
Parameter
Propagation delay single p-term
Propagation delay OR array
Direct input register clock setup time
-6
Min. Max.
-
5.5
-
6.0
2.2
-
-7
Min. Max.
5.5
6.0
2.2
-
Units
ns
ns
ns
DS552 (v1.1) May 5, 2007
www.xilinx.com
5
Product Specification