XA2C32A Datasheet, PDF (10/14 Pages) Xilinx, Inc – AEC-Q100 device qualification and full PPAP support

XA2C32A CoolRunner-II Automotive CPLD
Pin Descriptions (Continued)
Function Block
Macrocell
2
8
2
9
2
10
2
11
2
12
2
13
2
14
2
15
2
16
Notes:
1. GTS = global output enable, GSR = global set reset, GCK = global clock
2. GTS, GSR, and GCK pins can also be used for general purpose I/O.
VQG44
2
3
5
6
8
12
13
14
16
XA2C32A Global, JTAG, Power/Ground and No Connect Pins
Pin Type
TCK
TDI
TDO
TMS
Input Only
V_CCAUX (JTAG supply voltage)
Power internal (V_CC)
Power bank 1 I/O (V_CCIO1)
Power bank 2 I/O (V_CCIO2)
Ground
No connects
Total user I/O (includes dual function pins)
Notes:
1. All packages pin compatible with larger macrocell densities
R
I/O Bank
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
VQG44⁽¹⁾
11
9
24
10
18 (bank 2)
35
15
7
26
4,17,25
-
33
10
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DS552 (v1.1) May 5, 2007
Product Specification