XA2C32A Datasheet, PDF (2/14 Pages) Xilinx, Inc – AEC-Q100 device qualification and full PPAP support

XA2C32A CoolRunner-II Automotive CPLD
R
RealDigital Design Technology
Xilinx CoolRunner-II Automotive CPLDs are fabricated on a
0.18 micron process technology which is derived from lead-
ing edge FPGA product development. CoolRunner-II Auto-
motive CPLDs employ RealDigital, a design technique that
makes use of CMOS technology in both the fabrication and
design methodology. RealDigital design technology
employs a cascade of CMOS gates to implement sum of
products instead of traditional sense amplifier methodology.
Due to this technology, Xilinx CoolRunner-II Automotive
CPLDs achieve both high performance and low power oper-
ation.
Supported I/O Standards
The CoolRunner-II Automotive 32-macrocell device fea-
tures both LVCMOS and LVTTL I/O implementations. See
Table 1 for I/O standard voltages. The LVTTL I/O standard
is a general purpose EIA/JEDEC standard for 3.3V applica-
tions that use an LVTTL input buffer and Push-Pull output
buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V
applications. CoolRunner-II Automotive CPLDs are also
1.5V I/O compatible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XA2C32A
IOSTANDARD Attribute
LVTTL
Output
V_CCIO
3.3
LVCMOS33
3.3
LVCMOS25
2.5
LVCMOS18
1.8
LVCMOS15⁽¹⁾
1.5
(1) LVCMOS15 requires Schmitt-trigger inputs.
Input V_CCIO
3.3
3.3
2.5
1.8
1.5
10
5
0
0
50
100
150
Frequency (MHz)
Figure 1: I_CC vs Frequency
200
DS552_01_092006
Table 2: I_CC vs Frequency (LVCMOS 1.8V T_A = 25°C)⁽¹⁾
Frequency (MHz)
0
25
50
75
100
Typical I_CC (mA)
0.016
0.87
1.75
2.61
Notes:
1. 16-bit up/down, resettable binary counter (one counter per function block).
3.44
150
5.16
175
5.99
200
6.81
2
www.xilinx.com
DS552 (v1.1) May 5, 2007
Product Specification