WP433 Datasheet, PDF (7/8 Pages) Xilinx, Inc – Understanding and Mitigating

Summary
Summary
EOS and system-level ESD events are major causes of electrical failures, both in the
factory and in the field. The industry trend is towards reduction of ESD/EOS
immunity for 28 nm generations and beyond. ESD/EOS damage cannot be undone;
thus, the only cure is prevention. The first step in this endeavor is awareness of
ESD/EOS events; the second step is mitigation. The Xilinx support team offers advice
and consultation to customers on best practices and preventive measures.
Additional Resource
To see a summary of the reliability test data and results for Xilinx devices, see
UG116, Device Reliability Report. This report is updated four times per year.
References
1. Threshold, newsletter of the Electrostatic Discharge Association (ESDA), Vol.29 No.2
(March/April 2013), downloaded from http://esda.org/threshold_archives.cfm
2. Absolute Maximum Ratings (AMR) for 7 Series FPGAs. See Table 1, Absolute Maximum
Ratings in the data sheet for each of the 7 Series FPGA devices:
Artix®-7: Data sheet DS181, DC and AC Switching Characteristics.
Kintex®-7: Data sheet DS182, DC and AC Switching Characteristics.
Virtex®-7: Data sheet DS183, DC and AC Switching Characteristics.
3. XC Devices: Human Body Model (HBM): ANSI/ESDA/JEDEC JS-001
XA Devices: Human Body Model (HBM): AEC-Q100-002
4. XC Devices: Charged Device Model (CDM): JESD22-C101
XA Devices: Charged Device Model (CDM): AEC-Q100-011
5. Recommended ESD Target Levels for HBM/MM Qualification: see JEDEC, JEP155. Download
(with registration) at http://www.jedec.org/standards-documents/docs/jep-155.
6. CDM ESD Specifications and Requirements: see Industry Council on ESD Target Levels,
http://www.esdindustrycouncil.org/ic/en/
WP433 (v1.0) June 24, 2013
www.xilinx.com
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