WP433 Datasheet, PDF (2/8 Pages) Xilinx, Inc – Understanding and Mitigating

Introduction
Introduction
The scaling trend of the semiconductor industry, “Moore's Law,” leads to a reduction
in integrated circuit component-level ESD immunity. In previous technology
generations, a high level of integrated circuit (IC) component ESD immunity was often
able to protect against low-level system ESD and EOS events. Only high system-level
ESD and EOS events were able to damage a Xilinx device installed on a board. Such
events were usually readily recognized and eliminated. For advanced technology
nodes, 28 nm and beyond, the component-level ESD immunity is 50% less compared
to previous generations.
Each package pin of a Xilinx device has on-chip ESD protection elements. Power and
ground pins have the strongest ESD protection, while TX and RX SerDes pins are the
most vulnerable. These state-of-the-art high-speed I/Os are designed with the
smallest transistors available at the given technology node. Their ESD protection is
carefully optimized with respect to I/O performance; as a result, they have just enough
margin to pass a component-level ESD qualification for all package/silicon variants.
Per the ESD Association, which establishes ANSI-recognized standards for managing
ESD in manufacturing and in the electronics industry: “While significant progress has
been made over the past decades in the design, handling, and application of
electromagnetic-compatible (EMC) and ESD-protected electronic devices, progress
has been less than ideal in the minimization of EOS of such devices. The Industry
Council has recognized this deficiency and has decided to write a white paper on EOS
to help the industry understand the root causes of EOS and minimize it in electronic
devices.”[Ref 1]
Along these same lines, this Xilinx white paper aims to educate and help Xilinx
customers anticipate increasing system ESD and EOS event sensitivity, and to develop
adequate procedures to minimize them.
EOS/ESD Definitions
Electrostatic Discharge (ESD) is a sudden transfer of charge between objects at
different potentials. The charge is generated by triboelectrification or electrostatic
induction. Device survival of an ESD event is defined at two different levels:
Component-Level ESD Immunity is the ability of an IC to survive ESD events
related to IC package contact with any object. Events could be the result of human
touch, placement in or removal from a storage tray, pick-up or drop-off by a
robotic handler arm, placement in or removal from a tester socket, etc.
System-Level ESD Immunity is the ability of an IC mounted on a board to survive
ESD events caused by contacts of the board with any object. Such events could
come from a cable, human touch, physical placement of the board onto a metallic
surface, etc. System ESD events often can be an order of magnitude higher than
component-level events. By definition, then, the minimum system-level ESD
immunity of a device is the same as its component-level ESD immunity.
Electrical Overstress (EOS) is defined as operation of a device outside its absolute
maximum ratings (AMR).[Ref 2] EOS can cause damage, malfunction, or accelerated
aging leading to early failure of the device.
The scope of this white paper includes ESD and EOS as they relate to Xilinx devices of
the current 28 nm generation. The information described herein is also relevant to
2
www.xilinx.com
WP433 (v1.0) June 24, 2013