WP433 Datasheet, PDF (6/8 Pages) Xilinx, Inc – Understanding and Mitigating

Mitigation: System-Level ESD and EOS
EOS due to electromagnetic interference (EMI) on ground lines is often caused by
low-voltage DC motors or other circuits that draw large currents on startup. To
minimize the effect of EMI, a robust grounding concept, including filters, is essential.
High-level negative EMI can trigger transient latch-up and destroy the devices.
Mitigation: System-Level ESD and EOS
Practically all Xilinx customers have ESD programs implemented at the component
level. However, component-level ESD mitigation does not always protect the FPGA or
SoC after it has been mounted onto the system board. This white paper aims to
facilitate awareness of system-level ESD and EOS events.
Despite the industry trend towards reduction in component-level ESD immunity for
advanced technologies of the 28 nm generation and beyond (driven primarily by
increasing performance specifications), Xilinx has not only preserved but actually
increased the ESD immunity of power pins. Typically, the HBM level of power pins
was and is 3 kV, and CDM is about 400-500V or higher. At the same time, I/O pins
must be addressed; their ESD protection level is lower, with an HBM specification of
1 kV and a CDM of 200V or less.
See Figure 3 for a component and system ESD/EOS fishbone diagram that shows
examples of conditions or events that can cause electrical failures.
X-Ref Target - Figure 3
Misalignment
Assembly
Others
CDM
Component
Level
System
Level
CBE
CDE
Hot Plugging
Saturation
of Inductors Heat Dissipation
Instable/ Misinterpretation
Incomplete Tests of Standards Mishandling
System
Design
Testing
Software
Misorientation/
Misalignment
Hot Switching/
Plugging
Open/Shorted
Supply Lines
Tester
Artifacts
Misapplication
of Testers
Power Supply Accidental
Sequencing Power Fails
HBM
Misinsertion
Spec
Violations
ESD
SL-HBM
(IEC/ISO)
Others
Hot Plugging
Misapplication
EMI
Power-up/down
Fast Voltage
Transients
Inductive Switching
Poor Electrical Isolation
Other
Components
Overheating
Intermittent
Contacts
EOS
PCB Design
RF /
EMP
Lack of Filters Lack of
Shielding
Hard Switching
Note: EOS is not a
root cause but
a consequence.
Surge
Currents
Noise
Switching of Capacitors
Lack of Filters
Slow Voltage
Transients
Others
Source: Kaschani and Gaertner, 2011 EOS/ESD Symposium and ESDA EOS TR
Figure 3: Component and System ESD/EOS Fishbone Diagram
WP433_03_060313
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www.xilinx.com
WP433 (v1.0) June 24, 2013