WP433 Datasheet, PDF (1/8 Pages) Xilinx, Inc – Understanding and Mitigating

White Paper: 7 Series
WP433 (v1.0) June 24, 2013
Understanding and Mitigating
System-Level ESD and EOS Events
in Xilinx 7 Series Devices
By: James Karp, Michael Hart, and Tc Chai
The semiconductor industry’s scaling trend known
as “Moore’s Law” leads to a reduction in integrated
circuit component-level electrostatic discharge (ESD)
immunity, and consequently to exposure to
board-level/system-level ESD and electrical
overstress (EOS) events. Xilinx 7 series devices use
the most advanced 28 nm technology generation and
hence are subject to this trend.
This white paper describes the relationship between
FPGA component-level ESD and system-level EOS,
and provides industry-standard roadmaps and
references. Customer responsibilities are clearly
specified, and some recommended customer-side
approaches to EOS avoidance and mitigation are
described.
© Copyright 2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.
WP433 (v1.0) June 24, 2013
www.xilinx.com
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