WP433 Datasheet, PDF (4/8 Pages) Xilinx, Inc – Understanding and Mitigating

System-Level ESD
The roadmap for ESD (associated with the ITRS Roadmap for Semiconductors)
projects severe restrictions on achievable HBM and CDM ESD levels.[Ref 5][Ref 6]
Constraints from circuit design requirements (such as higher frequencies used by
SerDes and RF devices) can eventually reduce practical ESD HBM design levels to the
500V range. Similarly, the CDM level might be reduced to the 100V range.
Note: Machine Model (MM) scaling is not included in this white paper because many in the
industry now consider the MM requirement, with the exception of a very few limited
applications, to no longer be valid; indeed, there is a strong industry drive to eliminate it
from mainstream IC manufacturing ESD specifications.
For users, the trend of lowering component-level ESD immunity means that ESD
control in the production flow is absolutely necessary, and that CDM ESD control at
the factory must be critically improved.
Figure 2 shows a CDM roadmap that illustrates the evolution of CDM target voltage
levels since approximately 1980 as IC process dimensions steadily decreased in accord
with Moore’s Law.
X-Ref Target - Figure 2
CDM Target
Level
1000
750
(V)
500
1978 - 2008
2009 - 2014
CDM Control
Methods
2015
250
125
500 250 180 130 90
65
45
(nm)
28
20
16
WP433_02_061013
Figure 2: CDM Roadmap
System-Level ESD
After the FPGA or SoC is mounted onto the board, its on-chip ESD elements are still
present in the system, but their ESD protection capability is far below that of ESD
events the device can be exposed to on the board. HBM and CDM models are still
applicable at board level, yet they must be considered as an indication of “two point”
discharge (similar to HBM) or “one point” discharge (similar to CDM). A few
examples of the most damaging system-level ESD events are described in Charged
Board Event (CBE), Cable Discharge Event (CDE), and Ionizer-Related Discharge
Event sections.
4
www.xilinx.com
WP433 (v1.0) June 24, 2013