WP433 Datasheet, PDF (5/8 Pages) Xilinx, Inc – Understanding and Mitigating

Electrical Overstress
Charged Board Event (CBE)
CBE to a printed circuit board (PCB) is equivalent to CDM to the IC. CBE is the
discharge of accumulated static charges from a PCB when it makes contact with a
metal surface during board assembly or manufacturing. A PCB (as well as the ICs
mounted on it) can become statically charged when the PCB is transported during the
assembly process — for example, on a conveyor belt. Static discharge then happens
when the PCB comes into contact with a metal surface, damaging the IC on the board.
Cable Discharge Event (CDE)
Cables can be triboelectrically charged when removed from a bag or dragged across
another material. A low-voltage ESD generated when the charged cable is plugged in
can produce a CDE. The electrical signal produced by connecting charged cables to a
system connector can cause data corruption and soft failures as well as damage to the
external pins of ICs.
Ionizer-Related Discharge Event
Ionizers are primarily used for the reduction of particles and of damaging static
potentials in ESD-controlled work areas. One drawback, however, is that ionizers can
actually induce charging, due to ion polarity imbalance with voltage-type instruments
or to polarity imbalance referred to as space charging.
Some ESD events — for example, CBEs and CDEs, can be misdiagnosed as
power-induced electrical overstress, which is described in the Electrical Overstress
section.
Electrical Overstress
An FPGA or SoC on a board can be exposed to electrical overstress (EOS).[Ref 2]
Typical characteristics of EOS events:
• Their duration is longer than an ESD event (i.e., 1 µs or longer)
• EOS signal levels are typically much lower than ESD events
• EOS signals can be of any type: AC, DC, EMI, transients, and so forth. Unlike
ESD, EOS signals are often periodic and/or continuous.
EOS signals deliver significant amounts of energy to devices, and damage is often
manifested as massive meltdown. A device in the PCB assembly process can also
experience EOS during soldering or board test. A recently-formed EOS Group within
ESDA Standards is working on a document that describes EOS.[Ref 1]
EOS due to misapplication can destroy an FPGA or SoC by breaking down its internal
elements and melting the on-chip metallization. Most of these issues are due to severe
voltage over/under shoots caused by:
• Hot switching of relays (for example, connecting power to a pin through a relay
when the power supply is on and programmed to the desired voltage)
• Improper power sequencing
• Improper force/sense connections
• Poor board design for high dI/dt events
• Poorly chosen bias levels for continuity testing (for example, milliamperes of
current forced in test)
• Hot-plugged test cables
WP433 (v1.0) June 24, 2013
www.xilinx.com
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