WP433 Datasheet, PDF (3/8 Pages) Xilinx, Inc – Understanding and Mitigating

EOS/ESD Ownership
advanced integrated circuits other than FPGAs and SoCs; component ESD and
system-level EOS should be addressed for all parts of a system.
EOS/ESD Ownership
Xilinx is responsible for the shipment of devices (both FPGAs and SoCs) that meet the
Xilinx component-level ESD specification.
Customers are responsible for safely handling these devices in compliance with the
Xilinx component-level ESD specification.
Once a Xilinx device is mounted on a system board, the customer must establish its
own specification for system-level ESD and must implement the measures necessary
to meet this specification.
Customer EOS board design and protection must be sufficient to prevent Xilinx
devices from exceeding their published absolute maximum ratings.
Component-Level ESD Roadmap
Component-level ESD is traditionally evaluated in accordance with the Human Body
Model (HBM) [Ref 3] and the Charged Device Model (CDM) [Ref 4]. The practical
threat of an HBM event is significantly alleviated in FPGAs and SoCs because of their
close pin spacing and because of the much-reduced incidence of human handling in a
typical manufacturing flow. In contrast, CDM has become the primary real-world ESD
event, describing electrostatic charging of the FPGA and its rapid discharge during
automated handling, manufacturing, and assembly.
One of many examples is a device sliding down a shipping tube (charging) and hitting
a metal surface (discharging). The discharge current is limited only by the parasitic
impedance and capacitance of the device.
Figure 1 illustrates both HBM and CDM events.
X-Ref Target - Figure 1
R_P
CDUT
C_P
R
External Metal
WP433_01_052313
Figure 1: HBM and CDM ESD Events
WP433 (v1.0) June 24, 2013
www.xilinx.com
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