X24257 Datasheet, PDF (8/19 Pages) Xicor Inc. – 400kHz 2-Wire Serial EEPROM with Block Lock

X24257 – Preliminary Information
Figure 9. Random Read Sequence
S
S
Signals from
the Master
T
A
R
Slave
Address
Word Address
Byte 1
Word Address
Byte 0
T
A
R
Slave
Address
S
T
O
T
T
P
SDA Bus
S 1 0 1 0 0 S₁S₀ 0
S
1
P
t Signals from
the Slave
A
A
A
C
C
C
K
K
K
A
C
Data
K
c _{Figure 10. Sequential Read Sequence}
u _{Signals from}
d _{the Master}
Slave
Address
A
A
A
S
C
C
C
T
K
K
K
O
P
o ^{SDA Bus}
S ^S1^S0 1
P
r Signals from
the Slave
A
C
K
Data
(1)
Data
(2)
Data
(n–1)
Data
(n)
P^{(n is any integer greater than 1)}
CONTROL REGISTER (CR)
e ^{The Control Register is located in an area logically}
separated from the array and is only accessible via a
t byte write to the register address of FFFFH. The Con-
trol Register is physically part of the array.
e ^{The Control Register can only be modified by perform-}
ing a byte write operation directly to the address of the
l _{register and only one data byte is allowed for each reg-}
ister write operation. Prior to initiating a nonvolatile
o ^{write to the Control Register, the WEL and RWEL bits}
must be set using a two step process, with the whole
sequence requiring 3 steps.
s _{The user must issue a stop, after sending this byte to}
the register, to initiate the high voltage cycle that writes
b BP2, BP1, BP0 and WPEN to the nonvolatile bits. The
part will not acknowledge any data bytes written after
the first byte is entered. A stop must also be issued
O ^{after a volatile register write operation to put the device}
read. The master should supply a stop condition to be
consistent with the bus protocol, but a stop is not
required to end this operation. After the read of the CR,
the address counter contents are reset to zero, but the
user will be told these bits are undefined and instructed
to do a random read.
Table 1. Control Register
7
6
WPEN X
54 3
2
10
X BP1 BP0 RWEL WEL BP2
RWEL: Register Write Enable Latch
The RWEL bit must be set to “1” prior to a write to Con-
trol Register.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
into Standby. After a write to the CR, the address ^{tile latch that powers up in the LOW (disabled) state.}
counter contents are undefined.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
The state of the Control Register can be read by per- _{acknowledge will be issued after the Data Byte). The}
forming a random read at the address of the register at _{WEL bit is set by writing a “1” to the WEL bit and zeros}
any time. Only one byte is read by the register read _{to the other bits of the control register. Once set, WEL}
operation. The part will reset itself after the first byte is _{remains set until either it is reset to 0 (by writing a “0” to}
REV 1.1.1 10/15/00
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Characteristics subject to change without notice. 8 of 19