X24257 Datasheet, PDF (5/19 Pages) Xicor Inc. – 400kHz 2-Wire Serial EEPROM with Block Lock

X24257 – Preliminary Information
WRITE OPERATIONS
after the first data word is transferred, the master can
transmit up to sixty-three more words. The device will
Byte Write
respond with an acknowledge after the receipt of each
For a write operation, the device follows “3 byte” proto-
col, consisting of one Slave Address Byte, one Word
Address Byte 1, and the Word Address Byte 0, which
gives the master access to any one of the words in the
array. Upon receipt of the Word Address Byte 0, the
device responds with an acknowledge, and waits for
the first eight bits of data. After receiving the 8 bits of
the data byte, the device again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress
the device inputs are disabled and the device will not
respond to any requests from the master. The SDA pin
is at high impedance. See Figure 5.
Page Write
The device is capable of a 64 byte page write operation.
It is initiated in the same manner as the byte write
word, and then the byte address is internally incre-
mented by one. The page address remains constant.
When the counter reaches the end of the page, it “rolls
over” and goes back to the first byte of the current
t _{page. This means that the master can write 64-bytes to}
the page beginning at any byte. If the master begins
writing at byte 32, and loads 64-bytes, then the first
c _{32-bytes are written to bytes 32 through 63, and the}
last 16 words are written to bytes 0 through 31. After-
u ^{wards, the address counter would point to byte 32. If the}
master writes more than 64 bytes, then the previously
loaded data is overwritten by the new data, one byte at
d a time.
The master terminates the data byte loading by issuing
o ^{a stop condition, which causes the device to begin the}
nonvolatile write cycle. As with the byte write operation,
r all inputs are disabled until completion of the internal
write cycle. Refer to Figure 6 for the address, acknowl-
P^{edge, and data transfer sequence.}
operation; but instead of terminating the write operation
Figure 5. Byte Write Sequence
e _{Signals from}
t ^{the Master}
SDA Bus
le Signals from
the Slave
S
T
A
R
Slave
Address
T
Word Address
Byte 1
Word Address
Byte 0
S 1 0 1 0 0 S1S0 0
A
A
A
C
C
C
K
K
K
o _{Figure 6. Page Write Sequence}
s _{Signals from}
b ^{the Master}
O^{SDA Bus}
S
T
A
R
Slave
Address
T
Word Address
Byte 1
Word Address
Byte 0
S 1 0 1 0 0 S₁S₀ 0
A
A
A
Data
(0)
S
Data
T
O
P
P
A
C
K
(0 ≤ n ≤ 64)
Data
S
(n)
T
O
P
P
A
A
Signals from
C
C
C
C
C
the Slave
K
K
K
K
K
REV 1.1.1 10/15/00
www.xicor.com
Characteristics subject to change without notice. 5 of 19