X24257 Datasheet, PDF (10/19 Pages) Xicor Inc. – 400kHz 2-Wire Serial EEPROM with Block Lock

X24257 – Preliminary Information
Write Protect Enable Bit—WPEN (Nonvolatile)
Control Register, including the Block Protect bits and
The Write Protect (WP) pin and the Write Protect ^{the WPEN bit itself, as well as to the block sections in}
Enable (WPEN) bit in the Control Register control the ^{the memory array. Only the sections of the memory}
Programmable Hardware Write Protect feature. Hard-
ware Write Protection is enabled when the WP pin is
HIGH and the WPEN bit is HIGH, and disabled when
either the WP pin is LOW. When the chip is Hardware
t _{Write Protected, nonvolatile writes are disabled to the}
array that are not block protected can be written. Note
that since the WPEN bit is write protected, it cannot be
changed back to a LOW state; so write protection is
enabled as long as the WP pin is held HIGH.
c _{Table 3. Write Protect Enable Bit and WP Pin Function}
Memory Array Not Memory Array
u ^{WP WPEN Block Protected Block Protected}
LOW
X
Writes OK
Writes Blocked
d ^HIGH
0
Writes OK
Writes Blocked
HIGH
1
Writes OK
Writes Blocked
Block Lock Bits
Writes OK
Writes OK
Writes Blocked
WPEN Bit
Writes OK
Writes OK
Writes Blocked
Protection
Software
Software
Hardware
o _{Unused Bits}
r _{Bits 5 & 6 are unused. All writes to the Control Register}
must have a zero in these bit positions. The Data Byte
P ^{output during a Control Register read will contain zeros}
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
in these bit locations.
Writing to the Control Register
e ^{Changing any of the nonvolatile bits of the control reg-}
ister requires the following steps:
t – Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
e ^{there is no delay after the write. (Operation pre-}
ceeded by a start and ended with a stop).
l – Write a 06H to the Control Register to set both the
Register Write Enable Latch (RWEL) and the WEL
o ^{bit. This is also a volatile cycle. The zeros in the data}
byte are required. (Operation preceeded by a start
and ended with a stop).
s _{– Write a value to the Control Register that has all the}
control bits set to the desired state, with the WEL bit
b set to ‘1’ and the RWEL bit set to ‘0’. This can be
represented as n00s t01r in binary, where n is the
WPEN bit and rst are the BP2-BP0 bits. (Operation
O^{preceeded by a start and ended with a stop). Since}
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile
bits to 0 and clear the RWEL bit. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.
this is nonvolatile write cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and the
sequence must be repeated to change the nonvola-
tile bits again. If bit 2 is set to ‘1’ in this third step
(n00s t11r) then the RWEL bit remains set and the
WPEN, BP2, BP1 and BP0 bits remain unchanged.
REV 1.1.1 10/15/00
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Characteristics subject to change without notice. 10 of 19