X24257 Datasheet, PDF (12/19 Pages) Xicor Inc. – 400kHz 2-Wire Serial EEPROM with Block Lock

X24257 – Preliminary Information
CAPACITANCE T_A = +25°C, f = 1MHz, V_CC = 5V
Symbol
Parameter
Max.
Unit
Test Conditions
C_I/O⁽³⁾
C_IN⁽³⁾
Input/Output Capacitance (SDA)
Input Capacitance (S₀, S₁, S₂, SCL, WP)
8
pF
6
pF
V_I/O = 0V
V_IN = 0V
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
t _{Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.}
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; t_WC after a stop that initiates a
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
c (3) V_IL Min. and V_IH Max. are for reference only and are not tested.
A.C. CONDITIONS OF TEST
u _{Input pulse levels}
d ^{Input rise and fall times}
Input and output timing levels
o ^{Output load}
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC X 0.5
Standard output load
EQUIVALENT A.C. LOAD CIRCUIT
Output
5V
1.53KΩ
for V_OL = 0.4V
I_OL = 3mA
Pr ^100pF
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read & Write Cycle Limits
te Symbol
f_SCL
e ^tIN
l ^tAA
t_BUF
t_LOW
o _tHIGH
t_SU:STA
s _tHD:STA
t_SU:DAT
b _tHD:DAT
t_SU:STO
O^tDH
Parameter
SCL clock frequency
Pulse width suppression time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW period
Clock HIGH period
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
Data output hold time
V_CC 2.5V
Min.
Max.
0
400
50
0.1
0.9
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
t_R
SDA and SCL rise time
20 + .1Cb⁽³⁾ 300
ns
t_F
SDA and SCL fall time
20 + .1Cb⁽³⁾ 300
ns
t_{SU:S0, S1, S2, WP} S0, S1, S2, and WP Setup Time
0.6
ns
t_{HD:S0, S1, S2, WP} S0, S1, S2, and WP Hold Time
0
ns
Cb
Capacitive load for each bus line
400 pF
REV 1.1.1 10/15/00
www.xicor.com
Characteristics subject to change without notice. 12 of 19