X24257 Datasheet, PDF (4/19 Pages) Xicor Inc. – 400kHz 2-Wire Serial EEPROM with Block Lock

X24257 – Preliminary Information
Figure 3. Acknowledge Response From Receiver
SCL from
Master
1
Data Output
from Transmitter
Data Output
fromReceiver
Start
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits of
the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 2 bits are the
device select bits S₀ and S₁. This allows up to 4
devices to share a single bus. These bits are compared
8
9
uct _Acknowledge
d _{Figure 4. Device Addressing}
oDevice Type
Identifier
Device
Select
Pr^{1 0 1 0 0 S1 S0 R/W}
to the S₀ and S₁ device select input pins. The last bit of
the Slave Address Byte defines the operation to be
performed. When the R/W bit is a one, then a read
operation is selected. When it is zero then a write oper-
e _{ation is selected. Refer to Figure 4. After loading the}
Slave Address Byte from the SDA bus, the device com-
t _{pares the device type bits with the value “1010” and the}
device select bits with the status of the device select
e ^{input pins. If the compare is not successful, no}
acknowledge is output during the ninth clock cycle and
l _{the device returns to the standby mode.}
On power up the internal address is undefined, so the
o _{first read or write operation must supply an address.}
The word address is either supplied by the master or
s _{obtained from an internal counter, depending on the}
operation. The master must supply the two Word
b ^{Address Bytes as shown in Figure 4.}
The internal organization of the E² array is 512 pages
by 64 bytes per page. The page address is partially
O ^{contained in the Word Address Byte 1 and partially in}
Slave Address Byte
High Order Word Address
* A14 A13 A12 A11 A10 A9 A8
X24257 Word Address Byte 1
*This bit is 0 for access to the array and
1 for access to the Control Register
Low Order Word Address
A7 A6 _A5 A4 A3 A2 A1 A0
Word Address Byte 0
D7 D6 D5 D4 D3 D2 D1 D0
Data Byte
bits 7 through 6 of the Word Address Byte 0. The byte
address is contained in bits 5 through 0 of the Word
Address Byte 0. See Figure 4.
REV 1.1.1 10/15/00
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Characteristics subject to change without notice. 4 of 19