X24257 Datasheet, PDF (7/19 Pages) Xicor Inc. – 400kHz 2-Wire Serial EEPROM with Block Lock

X24257 – Preliminary Information
READ OPERATIONS
Random Read
Read operations are initiated in the same manner as ^{Random read operation allows the master to access}
write operations with the exception that the R/W bit of ^{any memory location in the array. Prior to issuing the}
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
t _{Current Address Read}
Internally, the device contains an address counter that
c _{maintains the address of the last word read or written}
incremented by one. After a read operation from the
last address in the array, the counter will “roll over” to
u _{the first address in the array. After a write operation to}
the last address in a given page, the counter will “roll
d ^{over” to the first address on the same page.}
Upon receipt of the Slave Address Byte with the R/W bit
o ^{set to one, the device issues an acknowledge and then}
transmits the eight bits of the Data Byte. The master ter-
r ^{minates the read operation when it does not respond}
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 8 for the
P ^{address, acknowledge, and data transfer sequence.}
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
e _{tion during the ninth cycle or hold SDA HIGH during}
the ninth clock cycle and then issue a stop condition.
t _{Figure 8. Current Address Read Sequence}
e _S
l Signals from
the Master
T
A
R
Slave
Address
S
T
O
T
P
o _{SDA Bus}
S 1 0 1 0 0 S₁S₀ 1
P
s ^{Signals from}
b ^{the Slave}
A
C
Data
K
Slave Address Byte with the R/W bit set to one, the
master must first perform a “Dummy” write operation.
The master issues the start condition and the Slave
Address Byte with the R/W bit low, receives an
acknowledge, then issues the Word Address Byte 1,
receives another acknowledge, then issues the Word
Address Byte 0. After the device acknowledges receipt
of the Word Address Byte 0, the master issues another
start condition and the Slave Address Byte with the R/W
bit set to one. This is followed by an acknowledge and
then eight bits of data from the device. The master ter-
minates the read operation by not responding with an
acknowledge and then issuing a stop condition. Refer
to Figure 9 for the address, acknowledge, and data
transfer sequence.
The device will perform a similar operation called “Set
Current Address” if a stop is issued instead of the sec-
ond start shown in Figure 9. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this oper-
ation is that the new address is loaded into the address
counter, but no data is output by the device.
The next Current Address Read operation will read
from the newly loaded address.
Sequential Read
Sequential reads can be initiated as either a current
address read or random read. The first Data Byte is
transmitted as with the other modes; however, the
master now responds with an acknowledge, indicating
it requires additional data. The device continues to out-
put data for each acknowledge received. The master ter-
minates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
O
address counter for read operations increments
through all byte addresses, allowing the entire memory
contents to be read during one operation. At the end of
the address space the counter “rolls over” to address
0000h and the device continues to output data for each
acknowledge received. Refer to Figure 10 for the
acknowledge and data transfer sequence.
REV 1.1.1 10/15/00
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Characteristics subject to change without notice. 7 of 19